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MB91460D Series
Feature MB91V460A MB91F465DA MB91F467DA MB91F467DB
External Interrupts NMI Interrupts
16 ch 1 ch
14 ch -
14 ch -
SMC LCD controller (40x4)
6 ch 1 ch
6 ch -
6 ch -
ADC (10 bit) Alarm Comparator
32 ch 2 ch
24 ch 1 ch
24 ch 1 ch
Supply Supervisor (low voltage detection) Clock Supervisor
yes yes
yes yes
yes yes
Main clock oscillator Sub clock oscillator RC Oscillator PLL
4MHz 32kHz 100kHz x 20
4MHz 32kHz 100kHz / 2MHz x 25
4MHz 32kHz 100kHz / 2MHz x 24
DSU4 EDSU
yes yes (32 BP)
*1
yes (16 BP)
*1
yes (16 BP) *1
Supply Voltage Regulator Power Consumption Temperature Range (Ta)
3V / 5V yes n.a. 0..70 C
3V / 5V yes <1W -40..105 C
3V / 5V yes <1W -40..105 C
Package
BGA660
QFP208
QFP208
Power on to PLL run Flash Download Time
< 20 ms n.a.
< 20 ms < 5 sec. typical
< 20 ms < 6 sec typical
*1 : MPU channels use EDSU breakpoint registers (shared operation between MPU and EDSU).
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MB91460D Series
NOITP RCSED
1. MB91F465DA, 7 x
Pin no. 2 to 9 10 to 17 18 to 25 28 to 35 36 to 43 44, 45 46 to 49 50 51 54 55 56 to 59 60, 61 62 63 64 65 in name P I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O circuit type* A A A A A A A A A A A A A A A A A Function General-purpose input/output ports Signal pins of external data bus (bit16 to bit23) General-purpose input/output ports Signal pins of external data bus (bit24 to bit31) General-purpose input/output ports Signal pins of external address bus (bit0 to bit7) General-purpose input/output ports Signal pins of external address bus (bit8 to bit15) General-purpose input/output ports Signal pins of external address bus (bit16 to bit23) General-purpose input/output ports Signal pins of external address bus (bit24, bit25) General-purpose input/output ports External write strobe output pins General-purpose input/output port External read strobe output pin General-purpose input/output port External bus release reception output pin General-purpose input/output port External bus release request input pin General-purpose input/output port External ready input pin General-purpose input/output ports Chip select output pins General-purpose input/output ports Chip select output pins General-purpose input/output port Address strobe output pin General-purpose input/output port Burst address advance output pin General-purpose input/output port Write enable output pin General-purpose input/output port Clock output pin for memory (Continued) DS07-16612-2E 7
P01_0 to P01_7 D16 to D23 P00_0 to P00_7 D24 to D31 P07_0 to P07_7 A0 to A7 P06_0 to P06_7 A8 to A15 P05_0 to P05_7 A16 to A23 P04_0, P04_1 A24, A25 P08_0 to P08_3 WRX0 to WRX3 P08_4 RDX P08_5 BGRNTX P08_6 BRQ P08_7 RDY P09_0 to P09_3 CSX0 to CSX3 P09_6, P09_7 CSX6, CSX7 P10_1 ASX P10_2 BAAX P10_3 WEX P10_4 MCLKO
MB91460D Series
(Continued) Pin no. 66 67 68 70 71 72 73 74 75 76 77 83 to 86 in name P P10_5 MCLKI P10_6 MCLKE MONCLK MD_2 MD_1 MD_0 INITX X1A X0A X1 X0 P24_0 to P24_3 INT0 to INT3 P24_4 87 INT4 SDA2 P24_5 88 INT5 SCL2 P24_6 89 INT6 SDA3 P24_7 90 INT7 SCL3 P23_0 91 RX0 INT8 92 P23_1 TX0 P23_2 93 RX1 INT9 I/O A I/O A I/O A I/O C I/O C I/O C I/O C I/O I/O I/O O I I I I I/O O/I circuit type* A A M G G G H J2 J2 J1 J1 A External reset input pin Sub clock (oscillation) output Sub clock (oscillation) input Clock (oscillation) output Clock (oscillation) input General-purpose input/output ports External interrupt input pins General-purpose input/output port External interrupt input pin I2C bus DATA input/output pin General-purpose input/output port External interrupt input pin I2C bus clock input/output pin General-purpose input/output port External interrupt input pin I2C bus DATA input/output pin General-purpose input/output port External interrupt input pin I2C bus clock input/output pin General-purpose input/output port RX input pin of CAN0 External interrupt input pin General-purpose input/output port TX output pin of CAN0 General-purpose input/output port RX input pin of CAN1 External interrupt input pin (Continued) 8 DS07-16612-2E Mode setting pins Function General-purpose input/output port Clock input pin for memory General-purpose input/output port Clock enable signal pin for memory Clock monitor pin
MB91460D Series
(Continued) Pin no. 94 Pin name P23_3 TX1 P23_4 95 RX2 INT10 96 97 98 P23_5 TX2 P22_0 INT12 P22_2 INT13 P22_4 99 SDA0 INT14 100 P22_5 SCL0 P20_0 101 SIN2 AIN0 P20_1 102 SOT2 BIN0 P20_2 103 SCK2 ZIN0 CK2 106 107 P19_0 SIN4 P19_1 SOT4 P19_2 108 SCK4 CK4 I/O A I/O I/O A A I/O A I/O A I/O A I/O C I/O C I/O I/O I/O A A A I/O A I/O I/O I/O circuit type* A TX output pin of CAN1 General-purpose input/output port RX input pin of CAN2 External interrupt input pin General-purpose input/output port TX output pin of CAN2 General-purpose input/output port External interrupt input pin General-purpose input/output port External interrupt input pin General-purpose input/output port I2C bus data input/output pin External interrupt input pin General-purpose input/output port I2C bus clock input/output pin General-purpose input/output port Data input pin of USART2 Up/down counter input pin General-purpose input/output port Data output pin of USART2 Up/down counter input pin General-purpose input/output port Clock input/output pin of USART2 Up/down counter input pin External clock input pin of free-run timer 2 General-purpose input/output port Data input pin of USART4 General-purpose input/output port Data output pin of USART4 General-purpose input/output port Clock input/output pin of USART4 External clock input pin of free-run timer 4 (Continued) Function General-purpose input/output port
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(Continued) Pin no. 109 110 Pin name P19_4 SIN5 P19_5 SOT5 P19_6 111 SCK5 CK5 P18_0 112 SIN6 AIN2 P18_1 113 SOT6 BIN2 P18_2 114 SCK6 ZIN2 CK6 P18_4 115 SIN7 AIN3 P18_5 116 SOT7 BIN3 P18_6 117 SCK7 ZIN3 CK7 P15_0 to P15_3 118 to 121 OCU0 to OCU3 TOT0 to TOT3 P14_0 to P14_7 ICU0 to ICU7 122 to 129 TIN0 to TIN7 TTG8 to TTG11, TTG4/12 to TTG7/15 I/O A I/O A I/O A I/O A I/O A I/O A I/O A I/O A I/O A I/O I/O I/O I/O circuit type* A A Function General-purpose input/output port Data input pin of USART5 General-purpose input/output port Data output pin of USART5 General-purpose input/output port Clock input/output pin of USART5 External clock input pin of free-run timer 5 General-purpose input/output port Data input pin of USART6 Up/down counter input pin General-purpose input/output port Data output pin of USART6 Up/down counter input pin General-purpose input/output port Clock input/output pin of USART6 Up/down counter input pin External clock input pin of free-run timer 6 General-purpose input/output port Data input pin of USART7 Up/down counter input pin General-purpose input/output port Data output pin of USART7 Up/down counter input pin General-purpose input/output port Clock input/output pin of USART7 Up/down counter input pin External clock input pin of free-run timer 7 General-purpose input/output ports Output compare output pins Reload timer output pins General-purpose input/output ports Input capture input pins External trigger input pins of reload timer External trigger input pins of PPG timer (Continued) 10 DS07-16612-2E
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(Continued) Pin no. 132 to 135 136 to 139 Pin name I/O I/O I/O I/O circuit type* A A Function General-purpose input/output ports Output pins of PPG timer General-purpose input/output ports PPG timer output pins General-purpose input/output port I/O A Output pin of PPG timer SGA output pin of sound generator General-purpose input/output port I/O A Output pin of PPG timer SGO output pin of sound generator General-purpose input/output port I/O A Output pin of PPG timer Pulse frequency modulator output pin General-purpose input/output port I/O I I/O A N B PPG timer output pin A/D converter external trigger input pin Alarm comparator input pin General-purpose input/output ports Analog input pins of A/D converter General-purpose input/output port I/O F Controller output pin of Stepper motor Analog input pin of A/D converter General-purpose input/output port I/O F Controller output pin of Stepper motor Analog input pin of A/D converter General-purpose input/output port I/O F Controller output pin of Stepper motor Analog input pin of A/D converter General-purpose input/output port I/O F Controller output pin of Stepper motor Analog input pin of A/D converter General-purpose input/output port I/O F Controller output pin of Stepper motor Analog input pin of A/D converter (Continued)
P17_4 to P17_7 PPG4 to PPG7 P16_0 to P16_3 PPG8 to PPG11 P16_4 PPG12 SGA P16_5
140
141
PPG13 SGO P16_6
142
PPG14 PFM P16_7
143 147 148 to 155
PPG15 ATGX ALARM_0 P29_0 to P29_7 AN0 to AN7 P27_0 SMC1P0 AN16 P27_1
158
159
SMC1M0 AN17 P27_2
160
SMC2P0 AN18 P27_3
161
SMC2M0 AN19 P27_4
164
SMC1P1 AN20
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(Continued) Pin no. Pin name P27_5 165 SMC1M1 AN21 P27_6 166 SMC2P1 AN22 P27_7 167 SMC2M1 AN23 P26_0 168 SMC1P2 AN24 P26_1 169 SMC1M2 AN25 P26_2 170 SMC2P2 AN26 P26_3 171 SMC2M2 AN27 P26_4 174 SMC1P3 AN28 P26_5 175 SMC1M3 AN29 P26_6 176 SMC2P3 AN30 P26_7 177 SMC2M3 AN31 I/O F I/O F I/O F I/O F I/O F I/O F I/O F I/O F I/O F I/O F I/O F I/O I/O circuit type* Function General-purpose input/output port Controller output pin of Stepper motor Analog input pin of A/D converter General-purpose input/output port Controller output pin of Stepper motor Analog input pin of A/D converter General-purpose input/output port Controller output pin of Stepper motor Analog input pin of A/D converter General-purpose input/output port Controller output pin of Stepper motor Analog input pin of A/D converter General-purpose input/output port Controller output pin of Stepper motor Analog input pin of A/D converter General-purpose input/output port Controller output pin of Stepper motor Analog input pin of A/D converter General-purpose input/output port Controller output pin of Stepper motor Analog input pin of A/D converter General-purpose input/output port Controller output pin of Stepper motor Analog input pin of A/D converter General-purpose input/output port Controller output pin of Stepper motor Analog input pin of A/D converter General-purpose input/output port Controller output pin of Stepper motor Analog input pin of A/D converter General-purpose input/output port Controller output pin of Stepper motor Analog input pin of A/D converter (Continued)
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[Power supply/Ground pins] Pin no. Pin name 1, 27, 53, 69, 79, 105, 131, 157, 188 163, 173, 183 26, 52 78, 104, 130, 156 162, 172, 182 81, 82 144 146 145 80 VSS5 HVSS5 VDD35 VDD5 HVDD5 VDD5R AVSS5 AVCC5 AVRH5 VCC18C Supply
I/O Ground pins
Function
Ground pins for Stepper motor controller Power supply pins for external data bus Power supply pins Power supply pins for Stepper motor controller Power supply pins for internal regulator Analog ground pin for A/D converter Power supply pin for A/D converter Reference power supply pin for A/D converter Capacitor connection pin for internal regulator
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S E P TY I U C R O /
Type A Circuit
pull-up control driver strength control data line
Remarks CMOS level output (programmable IOL = 5mA, IOH = -5mA and IOL = 2mA, IOH = -2mA) 2 different CMOS hysteresis inputs with input shutdown function Automotive input with input shutdown function TTL input with input shutdown function Programmable pull-up resistor: 50k approx.
pull- down control R CMOS hysteresis type1
CMOS hysteresis type2
Automotive inputs
TTL input standby control for input shutdown
B
pull-up control driver strength control data line
CMOS level output (programmable IOL = 5mA, IOH = -5mA and IOL = 2mA, IOH = -2mA) 2 different CMOS hysteresis inputs with input shutdown function Automotive input with input shutdown function TTL input with input shutdown function Programmable pull-up resistor: 50k approx. Analog input
pull- down control R CMOS hysteresis type1
CMOS hysteresis type2
Automotive inputs
TTL input standby control for input shutdown analog input
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Type C Circuit
pull-up control
Remarks CMOS level output (IOL = 3mA, IOH = -3mA) 2 different CMOS hysteresis inputs with input shutdown function Automotive input with input shutdown function TTL input with input shutdown function Programmable pull-up resistor: 50k approx.
data line
pull- down control R CMOS hysteresis type1
CMOS hysteresis type2
Automotive inputs
TTL input standby control for input shutdown
D
pull-up control
data line
CMOS level output (IOL = 3mA, IOH = -3mA) 2 different CMOS hysteresis inputs with input shutdown function Automotive input with input shutdown function TTL input with input shutdown function Programmable pull-up resistor: 50k approx. Analog input
pull- down control R CMOS hysteresis type1
CMOS hysteresis type2
Automotive inputs
TTL input standby control for input shutdown analog input
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Type E Circuit
pull-up control driver strength control data line
Remarks CMOS level output (programmable IOL = 5mA, IOH = -5mA and IOL = 2mA, IOH = -2mA, and IOL = 30mA, IOH = -30mA) 2 different CMOS hysteresis inputs with input shutdown function Automotive input with input shutdown function TTL input with input shutdown function Programmable pull-up resistor: 50k approx.
pull- down control R CMOS hysteresis type1
CMOS hysteresis type2
Automotive inputs
TTL input standby control for input shutdown
F
pull-up control driver strength control data line
pull- down control R CMOS hysteresis type1
CMOS level output (programmable IOL = 5mA, IOH = -5mA and IOL = 2mA, IOH = -2mA, and IOL = 30mA, IOH = -30mA) 2 different CMOS hysteresis inputs with input shutdown function Automotive input with input shutdown function TTL input with input shutdown function Programmable pull-up resistor: 50k approx. Analog input
CMOS hysteresis type2
Automotive inputs
TTL input standby control for input shutdown analog input
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MB91460D Series
Type G
R Hysteresis inputs
Circuit
Remarks Mask ROM and EVA device: CMOS Hysteresis input pin Flash device: CMOS input pin 12 V withstand (for MD [2:0]) CMOS Hysteresis input pin Pull-up resistor value: 50 k approx.
H
Pull-up Resistor R Hysteresis inputs
J1
X1
R
0 1
Xout
High-speed oscillation circuit: * Programmable between oscillation mode (external crystal or resonator connected to X0/X1 pins) and Fast external Clock Input (FCI) mode (external clock connected to X0 pin) * Feedback resistor = approx. 2 * 0.5 M. Feedback resistor is grounded in the center when the oscillator is disabled or in FCI mode.
R
FCI
X0
FCI or osc disable
J2
X1A
R
Xout
Low-speed oscillation circuit: * Feedback resistor = approx. 2 * 5 M. Feedback resistor is grounded in the center when the oscillator is disabled.
R
X0A
osc disable
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Type M
tri-state control data line
Circuit
Remarks CMOS level tri-state output (IOL = 5mA, IOH = -5mA)
N Analog input pin with protection
analog input line
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SECIV D GN L AH
1. Prev Iti g La ch-up
Latch-up may occur in a CMOS IC if a voltage higher than (VDD5, VDD35 or HVDD5) or less than (VSS5 or HVSS5) is applied to an input or output pin or if a voltage exceeding the rating is applied between the power supply pins and ground pins. If latch-up occurs, the power supply current increases rapidly, sometimes resulting in thermal breakdown of the device. Therefore, be very careful not to apply voltages in excess of the absolute maximum ratings.
2. Handling of unused input pins
If unused input pins are left open, abnormal operation may result. Any unused input pins should be connected to pull-up or pull-down resistor (2K to 10K) or enable internal pullup or pulldown resisters (PPER/PPCR) before the input enable (PORTEN) is activated by software. The mode pins MD_x can be connected to VSS5 or VDD5 directly. Unused ALARM input pins can be connected to AVSS5 directly.
3. Power supply pins
In MB91460D series, devices including multiple power supply pins and ground pins are designed as follows; pins necessary to be at the same potential are interconnected internally to prevent malfunctions such as latchup. All of the power supply pins and ground pins must be externally connected to the power supply and ground respectively in order to reduce unnecessary radiation, to prevent strobe signal malfunctions due to the ground level rising and to follow the total output current ratings. Furthermore, the power supply pins and ground pins of the MB91460D series must be connected to the current supply source via a low impedance. It is also recommended to connect a ceramic capacitor of approximately 0.1 F as a bypass capacitor between power supply pin and ground pin near this device. This series has a built-in step-down regulator. Connect a bypass capacitor of 4.7 F (use a X7R ceramic capacitator) to VCC18C pin for the regulator.
4. Crystal oscillator circuit
Noise in proximity to the X0 (X0A) and X1 (X1A) pins can cause the device to operate abnormally. Printed circuit boards should be designed so that the X0 (X0A) and X1 (X1A) pins, and crystal oscillator, as well as bypass capacitors connected to ground, are located near the device and ground. It is recommended that the printed circuit board layout be designed such that the X0 and X1 pins or X0A and X1A pins are surrounded by ground plane for the stable operation. Please request the oscillator manufacturer to evaluate the oscillational characteristics of the crystal and this device.
5. Notes on using external clock
When using the external clock, it is necessary to simultaneously supply the X0 (X0A) and the X1 (X1A) pins. In the described combination, X1 (X1A) should be supplied with a clock signal which has the opposite phase to the X0 (X0A) pins. At X0 and X1, a frequency up to 16 MHz is possible. (Continued)
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MB91460D Series
6. Mode pins (MD_x)
These pins should be connected directly to the power supply or ground pins. To prevent the device from entering test mode accidentally due to noise, minimize the lengths of the patterns between each mode pin and power supply pin or ground pin on the printed circuit board as possible and connect them with low impedance.
7. Notes on operating in PLL clock mode
If the oscillator is disconnected or the clock input stops when the PLL clock is selected, the microcontroller may continue to operate at the free-running frequency of the self-oscillating circuit of the PLL. However, this selfrunning operation cannot be guaranteed.
8. Pull-up control
The AC standard is not guaranteed in case a pull-up resistor is connected to the pin serving as an external bus pin.
9. Notes on PS register
As the PS register is processed in advance by some instructions, when the debugger is being used, the exception handling may result in execution breaking in an interrupt handling routine or the displayed values of the flags in the PS register being updated. As the microcontroller is designed to carry out reprocessing correctly upon returning from such an EIT event, the operation before and after the EIT always proceeds according to specification. * The following behavior may occur if any of the following occurs in the instruction immediately after a DIV0U/DIV0S instruction: (a) a user interrupt or NMI is accepted; (b) single-step execution is performed; (c) execution breaks due to a data event or from the emulator menu. 1. D0 and D1 flags are updated in advance. 2. An EIT handling routine (user interrupt/NMI or emulator) is executed. 3. Upon returning from the EIT, the DIV0U/DIV0S instruction is executed and the D0 and D1 flags are updated to the same values as those in 1. * The following behavior occurs wh en an ORCCR, STILM, MOV Ri,PS instruction is executed to enable a user interrupt or NMI source while that interr upt is in the active state. 1. The PS register is updated in advance. 2. An EIT handling routine (user interrupt/NMI or emulator) is executed. 3. Upon returning from the EIT, the above instructions are executed and the PS register is updated to the same value as in 1.
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MB91460D Series
REG UB D NO S T
1. ExecutioI f h R T C m a d
If single-step execution is used in an environment where an interrupt occurs frequently, the corresponding interrupt handling routine will be executed repeatedly to the exclusion of other processing. This will prevent the main routine and the handlers for low priority level interrupts from being executed (For example, if the time-base timer interrupt is enabled, stepping over the RETI instruction will always break on the first line of the time-base timer interrupt handler). Disable the corresponding interrupts when the corresponding interrupt handling routine no longer needs debugging.
2. Break function
If the range of addresses that cause a hardware break (including event breaks) is set to the address of the current system stack pointer or to an area that contains the stack pointer, execution will break after each instruction regardless of whether the user program actually contains data access instructions. To prevent this, do not set (word) access to the area containing the address of the system stack pointer as the target of the hardware break (including an event breaks).
3. Operand break
It may cause malfunctions if a stack pointer exists in the area which is set as the DSU operand break. Do not set the access to the areas containing the address of system stack pointer as a target of data event break.
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MARG ID KCOLB
1. MB91F465DA, 7 x
FR60 CPU core D-RAM 32 Kbytes Bit search Flash memory
1088 Kbytes (MB91F467Dx) 544 Kbytes (MB91F465DA) D-bus 32
Flash-Cache 8 Kbytes
I-bus 32
CAN 3 channels 32 <-> 16 bus adapter
RX0 to RX2 TX0 to TX2 BAAX WEX ASX RDX WRX0 to WRX3 BRQ MCLKE MCLKO MCLKI BGRNTX CSX0 to CSX3,CSX6,CSX7 A0 to A25 D0 to D31
ID-RAM
32 Kbytes (MB91F467Dx) 16 Kbytes (MB91F465DA)
Bus converter
External bus interface
DREQ0 DACKX0 DEOP0 DEOTX0
DMAC 5 channels Clock supervisor Clock control
R-bus 16
Clock modulator Clock monitor Interrupt controller External interrupt 14 channels
INT0 to INT10, INT12 to INT14 MONCLK
TTG8 to TTG11, TTG4/12 to TTG7/15 PPG4 to PPG15 TIN0 to TIN7 TOT0 to TOT3 CK2,CK4 to CK7
PPG timer 12 channels Reload timer 8 channels Free-run timer 8 channels Input capture 8 channels Output compare 4 channels Up/down counter 3 channels PFM timer 1 channel Alarm comparator 1 channel
LIN-USART 5 channels I2C 3 channels Real time clock
SIN2,SIN4 to SIN7 SOT2,SOT4 to SOT7 SCK2,SCK4 to SCK7 SDA0,SDA2,SDA3 SCL0,SCL2,SCL3
ICU0 to ICU7
OCU0 to OCU3 AIN0,AIN2,AIN3 BIN0,BIN2,BIN3 ZIN0,ZIN2,ZIN3 PFM
A/D converter 24 channels Stepper motor controller 6 channels Sound generator 1 channel
AN0 to AN7, AN16 to AN31 ATGX SMC1P0 to SMC1P5 SMC1M0 to SMC1M5 SMC2P0 to SMC2P5 SMC2M0 to SMC2M5 SGA SGO
ALARM_0
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TINU LOR C D A P
The FR family CPU is a high performance core that is designed based on the RISC architecture with advanced instructions for embedded applications.
1. Features
* Adoption of RISC architecture Basic instruction: 1 instruction per cycle * General-purpose registers: 32-bit x 16 registers * 4 Gbytes linear memory space * Multiplier installed 32-bit x 32-bit multiplication: 5 cycles 16-bit x 16-bit multiplication: 3 cycles * Enhanced interrupt processing function Quick response speed (6 cycles) Multiple-interrupt support Level mask function (16 levels) * Enhanced instructions for I/O operation Memory-to-memory transfer instruction Bit processing instruction Basic instruction word length: 16 bits * Low-power consumption Sleep mode/stop mode
2. Internal architecture
* The FR family CPU uses the Harvard architecture in which the instruction bus and data bus are independent of each other. * A 32-bit 16-bit buffer is connected to the 32-bit bus (D-bus) to provide an interface between the CPU and peripheral resources. * A Harvard Princeton bus converter is connected to both the I-bus and D-bus to provide an interface between the CPU and the bus controller.
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3. Programming model 3.1. Basic programming model
32 bits Initial value
R0 R1 ... ... ... ... XXXX XXXXH ... ... ... ... AC FP SP ... XXXX XXXXH 0000 0000H
General-purpose registers
R12 R13 R14 R15
Program counter Program status Table base register Return pointer System stack pointer User stack pointer Multiply & divide registers
PC RS TBR RP SSP USP MDH MDL ILM SCR CCR
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4. Registers 4.1. General-purpose register
32 bits Initial value
R0 R1 ... ... R12 R13 R14 R15 AC FP SP ... ... XXXX XXXXH ... ... ... ... ... XXXX XXXXH 0000 0000H
Registers R0 to R15 are general-purpose registers. These registers can be used as accumulators for computation operations and as pointers for memory access. Of the 16 registers, enhanced commands are provided for the following registers to enable their use for particular applications. R13 : Virtual accumulator R14 : Frame pointer R15 : Stack pointer Initial values at reset are undefined for R0 to R14. The value for R15 is 00000000H (SSP value).
4.2.
PS (Program Status)
This register holds the program status, and is divided into three parts, ILM, SCR, and CCR. All undefined bits (-) in the diagram are reserved bits. The read values are always "0". Write access to these bits is invalid. Bit position bit 31
bit 20 bit 16 bit 10 bit 8 bit 7 bit 0
ILM
SCR
CCR
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3. Flash access in CPU mode 3.1. 3.1.1. Flash configuration Flash memory map MB91F467Dx
Address 0014:FFFFh 0014:C000h 0014:BFFFh 0014:8000h 0014:7FFFh 0014:4000h 0014:3FFFh 0014:0000h 0013:FFFFh 0012:0000h 0011:FFFFh 0010:0000h 000F:FFFFh 000E:0000h 000D:FFFFh 000C:0000h 000B:FFFFh 000A:0000h 0009:FFFFh 0008:0000h 0007:FFFFh 0006:0000h 0005:FFFFh 0004:0000h addr+0 16bit read/write 32bit read/write 64bit read SA6 (8KB) SA7 (8KB)
SA4 (8KB)
SA5 (8KB) ROMS7
SA2 (8KB)
SA3 (8KB)
SA0 (8KB)
SA1 (8KB)
SA22 (64KB)
SA23 (64KB) ROMS6
SA20 (64KB)
SA21 (64KB)
SA18 (64KB)
SA19 (64KB)
ROMS5
SA16 (64KB)
SA17 (64KB)
ROMS4
SA14 (64KB)
SA15 (64KB)
ROMS3
SA12 (64KB)
SA13 (64KB)
ROMS2
SA10 (64KB)
SA11 (64KB)
ROMS1
SA8 (64KB) addr+1 addr+2 addr+3 addr+4
SA9 (64KB) addr+5 addr+6 addr+7
ROMS0
dat[31:16] dat[31:0]
dat[15:0]
dat[31:16] dat[31:0] dat[63:0]
dat[15:0]
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3.2. Flash access timing settings in CPU mode
The following tables list all settings for a given maximum Core Frequency (through the setting of CLKB or maximum clock modulation) for Flash read and write access.
3.2.1.
Flash read timing settings (synchronous read)
ATD 0 0 1 1 ALEH 0 0 1 1 EQ 0 1 3 3 WEXH WTC 1 2 4 4 not available on MB91F467Dx Remark to 24 MHz to 48 MHz to 96 MHz to 100 MHz
Core clock (CLKB)
3.2.2.
Flash write timing settings (synchronous write)
ATD 1 1 1 1 1 ALEH EQ WEXH 0 0 0 0 0 WTC 4 5 6 7 7 not available on MB91F467Dx Remark to 32 MHz to 48 MHz to 64 MHz to 96 MHz to 100 MHz
Core clock (CLKB)
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4.2. Pin connections in parallel programming mode
Resetting after setting the MD[2:0] pins to [111] will halt CPU functioning. At this time, the Flash memory's interface circuit enables direct control of the Flash memory unit from external pins by directly linking some of the signals to General Purpose Ports. Please see table below for signal mapping. In this mode, the Flash memory appears to the external pins as a stand-alone unit. This mode is generally set when writing/erasing using the parallel Flash programmer. In this mode, all operations of the 8.5 Mbits Flash memory's Auto Algorithms are available. Correspondence between MBM29LV400TC and Flash Memory Control Signals MB91F465DA, MB91F467Dx external pins MBM29LV400TC External pins RESET RY/BY BYTE WE OE CE A-1 A0 to A3 A4 to A7 A8 to A11 A12 to A15 A16 to A19 Internal control signal + control via interface circuit FR-CPU mode Flash memory mode FRSTX MD_2 MD_1 MD_0 RY/BYX BYTEX WEX OEX CEX ATDIN EQIN TESTX RDYI FA0 FA1 to FA4 FA5 to FA8 FA9 to FA12 Internal address bus FA13 to FA16 FA17 to FA20 Comment Normal function INITX P09_6 MD_2 MD_1 MD_0 P09_0 P09_2 P13_2 P13_1 P13_0 P25_7 P25_6 P09_3 P09_1 P25_5 P27_0 to P27_3 P27_4 to P27_7 P26_0 to P26_3 P26_4 to P26_7 P25_0 to P25_3 Pin number 73 60 70 71 72 56 58 191 190 189 187 186 59 57 185 158 to 161 164 to 167 168 to 171 174 to 177 178 to 181 Not needed on MB91F465DA; Set to `1' on MB91F467Dx Set to `0' Set to `0' Set to `1' Set to `0' Set to `0' Set to `1' Set to `1' Set to `1'
INITX FMCS:RDY bit Internally fixed to 'H'
FA21
P25_4
184
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37
MB91460D Series
6.3. Security Vector FSV2
The setting of the Flash Security Vector FSV2 bits [31:0] is responsible for the individual write protection of the 64 Kbytes sectors. It is only evaluated if write protection bit FSV1 [17] is set. Explanation of the bits in the Flash Security Vector FSV2[31:0] Enable Write Disable Write FSV2 bit Sector Protection Protection FSV2[0] FSV2[1] FSV2[2] FSV2[3] FSV2[4] FSV2[5] FSV2[6] FSV2[7] FSV2[8] FSV2[9] FSV2[10] FSV2[11] FSV2[12] FSV2[13] FSV2[14] FSV2[15] FSV2[31:16] SA8 (MB91F467Dx) SA9 (MB91F467Dx) SA10 (MB91F467Dx) SA11 (MB91F467Dx) SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 (MB91F467Dx) SA21 (MB91F467Dx) SA22 (MB91F467Dx) SA23 (MB91F467Dx) set to "0" set to "0" set to "0" set to "0" set to "0" set to "0" set to "0" set to "0" set to "0" set to "0" set to "0" set to "0" set to "0" set to "0" set to "0" set to "0" set to "0" set to "1" set to "1" set to "1" set to "1" set to "1" set to "1" set to "1" set to "1" set to "1" set to "1" set to "1" set to "1" set to "1" set to "1" set to "1" set to "1" set to "1" not available
Comment
Note : See section "Flash access in CPU mode" for an overview about the sector organisation of the Flash Memory.
40
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ACE SP Y ME OR
The FR family has 4 Gbytes of logical address space (232 addresses) available to the CPU by linear access. * Direct addressing area The following address space area is used for I/O. This area is called direct addressing area, and the address of an operand can be specified directly in an instruction. The size of directly addressable area depends on the length of the data being accessed as shown below. Byte data access : 000H to 0FFH Half word access : 000H to 1FFH Word data access : 000H to 3FFH
DS07-16612-2E
41
MB91460D Series
MAPSY EOR
1. MB91F465DA, 7 x
MB91F467Dx
00000000H 00000400H 00001000H 00002000H 00004000H 00006000H 00007000H 00008000H 00000000H I/O (direct addressing area) 00000400H I/O 00001000H DMA 00002000H 00004000H Flash-Cache (8 KBytes) 00006000H 00007000H Flash memory control 00008000H
MB91F465DA
I/O (direct addressing area) I/O DMA
Flash-Cache (8 KBytes)
Flash memory control
0000B000H 0000C000H 0000D000H
0000B000H Boot ROM (4 Kbytes) 0000C000H CAN 0000D000H
Boot ROM (4 Kbytes) CAN
00028000H 00028000H 00030000H 00038000H 00040000H D-RAM (0 wait, 32 Kbytes) ID-RAM (32 Kbytes) 00030000H 00034000H 00040000H 00080000H
D-RAM (0 wait, 32 Kbytes) ID-RAM (16 Kbytes)
External bus area
Flash memory (512 Kbytes) Flash memory (1088 Kbytes) 00100000H 00148000H 00150000H 00180000H External bus area 00500000H External data bus FFFFFFFFH FFFFFFFFH 00500000H External data bus 00150000H 00180000H External bus area
External bus area Flash memory (32 Kbytes)
Note:
Access prohibited areas
Note:
Access prohibited areas
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(Continued) Address Register +0 +1 +2 +3 RDR04/TDR04 [R/W] 00000000 FCR04 [R/W] 0001 - 000 RDR05/TDR05 [R/W] 00000000 FCR05 [R/W] 0001 - 000 RDR06/TDR06 [R/W] 00000000 FCR06 [R/W] 0001 - 000 RDR07/TDR07 [R/W] 00000000 FCR07 [R/W] 0001 - 000 Block
000060H
SCR04 [R/W, W] SMR04 [R/W, W] SSR04 [R/W, R] 00000000 00000000 00001000 ESCR04 [R/W] 00000X00 ECCR04 [R/W, R, W] -00000XX FSR04 [R] - - - 00000
000064H
LIN-USART 4 with FIFO
000068H
SCR05 [R/W, W] SMR05 [R/W, W] SSR05 [R/W, R] 00000000 00000000 00001000 ESCR05 [R/W] 00000X00 ECCR05 [R/W, R, W] -00000XX FSR05 [R] - - - 00000
00006CH
LIN-USART 5 with FIFO
000070H
SCR06 [R/W, W] SMR06 [R/W, W] SSR06 [R/W, R] 00000000 00000000 00001000 ESCR06 [R/W] 00000X00 ECCR06 [R/W, R, W] -00000XX FSR06 [R] - - - 00000
000074H
LIN-USART 6 with FIFO
000078H
SCR07 [R/W, W] SMR07 [R/W, W] SSR07 [R/W, R] 00000000 00000000 00001000 ESCR07 [R/W] 00000X00 ECCR07 [R/W, R, W] -00000XX BGR002 [R/W] 00000000 BGR004 [R/W] 00000000 BGR006 [R/W] 00000000 FSR07 [R] - - - 00000
00007CH 000080H 000084H 000088H 00008CH 000090H 000094H 000098H 00009CH
LIN-USART 7 with FIFO
Reserved BGR102 [R/W] 00000000 BGR104 [R/W] 00000000 BGR106 [R/W] 00000000 Reserved BGR105 [R/W] 00000000 BGR107 [R/W] 00000000 BGR005 [R/W] 00000000 BGR007 [R/W] 00000000
Reserved Baud rate Generator LIN-USART 2,4 to 7
PWC20 [R/W] - - - - - - XX XXXXXXXX Reserved PWC21 [R/W] - - - - - - XX XXXXXXXX Reserved
PWC10 [R/W] - - - - - - XX XXXXXXXX PWS20 [R/W] -0000000 PWS10 [R/W] - -000000
Stepper Motor 0
PWC11 [R/W] - - - - - - XX XXXXXXXX PWS21 [R/W] -0000000 PWS11 [R/W] - -000000
Stepper Motor 1
(Continued)
DS07-16612-2E
45
MB91460D Series
(Continued) Address 0000A0H 0000A4H 0000A8H 0000ACH 0000B0H 0000B4H 0000B8H 0000BCH 0000C0H 0000C4H 0000C8H 0000CCH 0000D0H 0000D4H 0000D8H 0000DCH to 000100H 000104H 000108H 000110H to 00012CH GCN11 [R/W] 00110010 00010000 GCN12 [R/W] 00110010 00010000 IBCR0 [R/W] 00000000 ITMKH0 [R/W] 00 - - - - 11 Reserved Register +0 +1 +2 +3 PWC22 [R/W] - - - - - - XX XXXXXXXX Reserved PWC23 [R/W] - - - - - - XX XXXXXXXX Reserved PWC24 [R/W] - - - - - - XX XXXXXXXX Reserved PWC25 [R/W] - - - - - - XX XXXXXXXX Reserved Reserved Reserved Reserved PWC0 [R/W] -00000-PWC2 [R/W] -00000-PWC4 [R/W] -00000-IBSR0 [R] 00000000 ITMKL0 [R/W] 11111111 IDAR0 [R/W] 00000000 PWC12 [R/W] - - - - - - XX XXXXXXXX PWS22 [R/W] -0000000 PWS12 [R/W] - -000000 Block
Stepper Motor 2
PWC13 [R/W] - - - - - - XX XXXXXXXX PWS23 [R/W] -0000000 PWS13 [R/W] - -000000
Stepper Motor 3
PWC14 [R/W] - - - - - - XX XXXXXXXX PWS24 [R/W] -0000000 PWS14 [R/W] - -000000
Stepper Motor 4
PWC15 [R/W] - - - - - - XX XXXXXXXX PWS25 [R/W] -0000000 Reserved Reserved Reserved PWS15 [R/W] - -000000 PWC1 [R/W] -00000-PWC3 [R/W] -00000-PWC5 [R/W] -00000--
Stepper Motor 5
Stepper Motor Control 0 to 5
Reserved ITBAH0 [R/W] - - - - - - 00 ISMK0 [R/W] 01111111 ICCR0 [R/W] 00011111 ITBAL0 [R/W] 00000000 ISBA0 [R/W] - 0000000 Reserved
Reserved
I2C 0
Reserved GCN21 [R/W] - - - - 0000 GCN22 [R/W] - - - - 0000
Reserved PPG Control 4 to 7 PPG Control 8 to 11 Reserved (Continued)
Reserved Reserved
Reserved
46
DS07-16612-2E
MB91460D Series
(Continued) Address 000130H 000134H 000138H 00013CH 000140H 000144H 000148H 00014CH 000150H 000154H 000158H 00015CH 000160H 000164H 000168H 00016CH Register +0 +1 +2 +3 PTMR04 [R] 11111111 11111111 PDUT04 [W] XXXXXXXX XXXXXXXX PTMR05 [R] 11111111 11111111 PDUT05 [W] XXXXXXXX XXXXXXXX PTMR06 [R] 11111111 11111111 PDUT06 [W] XXXXXXXX XXXXXXXX PTMR07 [R] 11111111 11111111 PDUT07 [W] XXXXXXXX XXXXXXXX PTMR08 [R] 11111111 11111111 PDUT08 [W] XXXXXXXX XXXXXXXX PTMR09 [R] 11111111 11111111 PDUT09 [W] XXXXXXXX XXXXXXXX PTMR10 [R] 11111111 11111111 PDUT10 [W] XXXXXXXX XXXXXXXX PTMR11 [R] 11111111 11111111 PDUT11 [W] XXXXXXXX XXXXXXXX P0TMCSRH [R/W] - 0 - 000 - 0 P0TMCSRL [R/W] - - - 00000 PCSR04 [W] XXXXXXXX XXXXXXXX PCNH04 [R/W] 0000000 PCNL04 [R/W] 000000 - 0 Block
PPG 4
PCSR05 [W] XXXXXXXX XXXXXXXX PCNH05 [R/W] 0000000 PCNL05 [R/W] 000000 - 0
PPG 5
PCSR06 [W] XXXXXXXX XXXXXXXX PCNH06 [R/W] 0000000 PCNL06 [R/W] 000000 - 0
PPG 6
PCSR07 [W] XXXXXXXX XXXXXXXX PCNH07 [R/W] 0000000 PCNL07 [R/W] 000000 - 0
PPG 7
PCSR08 [W] XXXXXXXX XXXXXXXX PCNH08 [R/W] 0000000 PCNL08 [R/W] 000000 - 0
PPG 8
PCSR09 [W] XXXXXXXX XXXXXXXX PCNH09 [R/W] 0000000 PCNL09 [R/W] 000000 - 0
PPG 9
PCSR10 [W] XXXXXXXX XXXXXXXX PCNH10 [R/W] 0000000 PCNL10 [R/W] 000000 - 0
PPG 10
PCSR11 [W] XXXXXXXX XXXXXXXX PCNH11 [R/W] 0000000 P1TMCSRH [R/W] - 0 - 000 - 0 PCNL11 [R/W] 000000 - 0 P1TMCSRL [R/W] - - - 00000
PPG 11
000170H
000174H 000178H 00017CH
P0TMRLR [W] XXXXXXXX XXXXXXXX P1TMRLR [W] XXXXXXXX XXXXXXXX Reserved
P0TMR [R] XXXXXXXX XXXXXXXX P1TMR [R] XXXXXXXX XXXXXXXX
PFM
Reserved (Continued) 47
DS07-16612-2E
MB91460D Series
(Continued) Address 000180H 000184H 000188H 00018CH 000190H 000194H 000198H 00019CH 0001A0H 0001A4 0001A8H 0001ACH 0001B0H Register +0 Reserved +1 ICS01 [R/W] 00000000 +2 Reserved +3 ICS23 [R/W] 00000000 Input Capture 0 to 3 Block
IPCP0 [R] XXXXXXXX XXXXXXXX IPCP2 [R] XXXXXXXX XXXXXXXX OCS01 [R/W] - - - 0 - - 00 0000 - - 00 OCCP0 [R/W] XXXXXXXX XXXXXXXX OCCP2 [R/W] XXXXXXXX XXXXXXXX SGCRH [R/W] 0000 - - 00 SGAR [R/W] 00000000 SGCRL [R/W] - - 0 - - 000 Reserved
IPCP1 [R] XXXXXXXX XXXXXXXX IPCP3 [R] XXXXXXXX XXXXXXXX OCS23 [R/W] - - - 0 - - 00 0000 - - 00 OCCP1 [R/W] XXXXXXXX XXXXXXXX OCCP3 [R/W] XXXXXXXX XXXXXXXX SGFR [R/W, R] XXXXXXXX XXXXXXXX SGTR [R/W] XXXXXXXX SGDR [R/W] XXXXXXXX
Output Compare 0 to 3
Sound Generator
ADERH [R/W] 00000000 00000000 ADCS1 [R/W] 00000000 ADCT1 [R/W] 00010000 Reserved ADCS0 [R/W] 00000000 ADCT0 [R/W] 00101100 ACSR0 [R/W] - 11XXX00
ADERL [R/W] 00000000 00000000 ADCR1 [R] 000000XX ADSCH [R/W] - - - 00000 ADCR0 [R] XXXXXXXX ADECH [R/W] - - - 00000 Alarm Comparator 0 A/D Converter
Reserved TMR0 [R] XXXXXXXX XXXXXXXX TMCSRH0 [R/W] - - - 00000 TMCSRL0 [R/W] 0 - 000000
TMRLR0 [W] XXXXXXXX XXXXXXXX Reserved TMRLR1 [W] XXXXXXXX XXXXXXXX Reserved TMRLR2 [W] XXXXXXXX XXXXXXXX Reserved
Reload Timer 0
0001B4H
0001B8H
TMR1 [R] XXXXXXXX XXXXXXXX TMCSRH1 [R/W] - - - 00000 TMCSRL1 [R/W] 0 - 000000 Reload Timer 1
0001BCH
0001C0H
TMR2 [R] XXXXXXXX XXXXXXXX TMCSRH2 [R/W] - - - 00000 TMCSRL2 [R/W] 0 - 000000
Reload Timer 2 (PPG 4, PPG 5) (Continued)
0001C4H
48
DS07-16612-2E
MB91460D Series
(Continued) Address 0001C8H Register +0 +1 +2 +3 TMRLR3 [W] XXXXXXXX XXXXXXXX Reserved TMRLR4 [W] XXXXXXXX XXXXXXXX Reserved TMRLR5 [W] XXXXXXXX XXXXXXXX Reserved TMRLR6 [W] XXXXXXXX XXXXXXXX Reserved TMRLR7 [W] XXXXXXXX XXXXXXXX Reserved TMR3 [R] XXXXXXXX XXXXXXXX TMCSRH3 [R/W] - - - 00000 TMCSRL3 [R/W] 0 - 000000 Block
Reload Timer 3 (PPG 6, PPG 7)
0001CCH
0001D0H
TMR4 [R] XXXXXXXX XXXXXXXX TMCSRH4 [R/W] - - - 00000 TMCSRL4 [R/W] 0 - 000000
Reload Timer 4 (PPG 8, PPG 9)
0001D4H
0001D8H
TMR5 [R] XXXXXXXX XXXXXXXX TMCSRH5 [R/W] - - - 00000 TMCSRL5 [R/W] 0 - 000000
Reload Timer 5 (PPG 10, PPG 11)
0001DCH
0001E0H
TMR6 [R] XXXXXXXX XXXXXXXX TMCSRH6 [R/W] - - - 00000 TMCSRL6 [R/W] 0 - 000000
Reload Timer 6 (PPG 12, PPG 13)
0001E4H
0001E8H
TMR7 [R] XXXXXXXX XXXXXXXX TMCSRH7 [R/W] - - - 00000 TMCSRL7 [R/W] 0 - 000000 TCCS0 [R/W] 00000000
Reload Timer 7 (PPG 14, PPG 15) (A/D Converter) Free Running Timer 0 (ICU 0, ICU 1)
0001ECH
0001F0H
TCDT0 [R/W] XXXXXXXX XXXXXXXX
Reserved
0001F4H
TCDT1 [R/W] XXXXXXXX XXXXXXXX
Reserved
TCCS1 [R/W] 00000000
Free Running Timer 1 (ICU 2, ICU 3)
0001F8H
TCDT2 [R/W] XXXXXXXX XXXXXXXX
Reserved
TCCS2 [R/W] 00000000
Free Running Timer 2 (OCU 0, OCU 1)
0001FCH
TCDT3 [R/W] XXXXXXXX XXXXXXXX
Reserved
TCCS3 [R/W] 00000000
Free Running Timer 3 (OCU 2, OCU 3) (Continued)
DS07-16612-2E
49
MB91460D Series
(Continued) Address 000200H 000204H 000208H 00020CH 000210H 000214H 000218H 00021CH 000220H 000224H 000228H to 00023CH 000240H 000244H to 0002CCH 0002D0H 0002D4H 0002D8H 0002DCH to 0002ECH TCDT4 [R/W] XXXXXXXX XXXXXXXX Reserved DMACR [R/W] 00 - - 0000 Register +0 +1 +2 +3 DMACA0 [R/W] 00000000 0000XXXX XXXXXXXX XXXXXXXX DMACB0 [R/W] 00000000 00000000 XXXXXXXX XXXXXXXX DMACA1 [R/W] 00000000 0000XXXX XXXXXXXX XXXXXXXX DMACB1 [R/W] 00000000 00000000 XXXXXXXX XXXXXXXX DMACA2 [R/W] 00000000 0000XXXX XXXXXXXX XXXXXXXX DMACB2 [R/W] 00000000 00000000 XXXXXXXX XXXXXXXX DMACA3 [R/W] 00000000 0000XXXX XXXXXXXX XXXXXXXX DMACB3 [R/W] 00000000 00000000 XXXXXXXX XXXXXXXX DMACA4 [R/W] 00000000 0000XXXX XXXXXXXX XXXXXXXX DMACB4 [R/W] 00000000 00000000 XXXXXXXX XXXXXXXX Reserved DMAC Block
Reserved
Reserved ICS045 [R/W] 00000000 ICS67 [R/W] 00000000
Reserved
Reserved
IPCP4 [R] XXXXXXXX XXXXXXXX IPCP6 [R] XXXXXXXX XXXXXXXX Reserved
IPCP5 [R] XXXXXXXX XXXXXXXX IPCP7 [R] XXXXXXXX XXXXXXXX
Input Capture 4 to 7
Reserved Free Running Timer 4 (ICU 4, ICU 5) (Continued)
0002F0H
Reserved
TCCS4 [R/W] 00000000
50
DS07-16612-2E
MB91460D Series
(Continued) Address Register +0 +1 +2 Reserved +3 TCCS5 [R/W] 00000000 TCCS6 [R/W] 00000000 TCCS7 [R/W] 00000000 UDCR0 [R] 00000000 UDCS0 [R/W] 00000000 Block Free Running Timer 5 (ICU 6, ICU 7) 0002F8H 0002FCH 000300H 000304H 000308H, 00030CH 000310H 000314H 000318H 00031CH 000320H 000324H to 00032CH 000330H 000334H 000338H 00033CH 000340H 000344H PTMR12 [R] 11111111 11111111 PDUT12 [W] XXXXXXXX XXXXXXXX PTMR13 [R] 11111111 11111111 PDUT13 [W] XXXXXXXX XXXXXXXX PTMR14 [R] 11111111 11111111 PDUT14 [W] XXXXXXXX XXXXXXXX GCN13 [R/W] 00110010 00010000 UDRC3 [W] 00000000 UDCCH2 [R/W] 00000000 UDCCH3 [R/W] 00000000 TCDT6 [R/W] XXXXXXXX XXXXXXXX TCDT7 [R/W] XXXXXXXX XXXXXXXX Reserved UDCCH0 [R/W] 00000000 UDRC0 [W] 00000000 UDCCL0 [R/W] 00001000 Reserved Reserved Reserved Reserved Free Running Timer 6 Free Running Timer 7 Up/Down Counter 0 Reserved UDCR2 [R] 00000000 UDCS2 [R/W] 00000000 UDCS3 [R/W] 00000000 Reserved GCN23 [R/W] - - - - 0000 PPG Control 12 to 15 Reserved PCSR12 [W] XXXXXXXX XXXXXXXX PCNH12 [R/W] 0000000 PCNL12 [R/W] 000000 - 0 Up/Down Counter 2 to 3
0002F4H
TCDT5 [R/W] XXXXXXXX XXXXXXXX
Reserved UDRC2 [W] 00000000 UDCCL2 [R/W] 00001000 UDCCL3 [R/W] 00001000 UDCR3 [R] 00000000 Reserved Reserved
Reserved Reserved
Reserved
PPG 12
PCSR13 [W] XXXXXXXX XXXXXXXX PCNH13 [R/W] 0000000 PCNL13 [R/W] 000000 - 0
PPG 13
PCSR14 [W] XXXXXXXX XXXXXXXX PCNH14 [R/W] 0000000 PCNL14 [R/W] 000000 - 0
PPG 14
(Continued)
DS07-16612-2E
51
MB91460D Series
(Continued) Address 000348H 00034CH 000350H to 000364H 000368H 00036CH 000370H 000374H 000378H 00037CH 000380H to 00038CH ROMS [R] 000390H 000394H to 0003ECH 0003F0H 0003F4H 0003F8H 0003FCH 000400H to 00043CH
11111111 00000000 (MB91F467Dx) 11111111 01000011 (MB91F465DA)
Register +0 +1 +2 +3 PTMR15 [R] 11111111 11111111 PDUT15 [W] XXXXXXXX XXXXXXXX PCSR15 [W] XXXXXXXX XXXXXXXX PCNH15 [R/W] 0000000 Reserved IBCR2 [R/W] 00000000 ITMKH2 [R/W] 00 - - - - 11 Reserved IBCR3 [R/W] 00000000 ITMKH3 [R/W] 00 - - - - 11 Reserved IBSR2 [R] 00000000 ITMKL2 [R/W] 11111111 IDAR2 [R/W] 00000000 IBSR3 [R] 00000000 ITMKL3 [R/W] 11111111 IDAR3 [R/W] 00000000 ITBAH2 [R/W] - - - - - - 00 ISMK2 [R/W] 01111111 ICCR2 [R/W] 00011111 ITBAH3 [R/W] - - - - - - 00 ISMK3 [R/W] 01111111 ICCR3 [R/W] 00011111 ITBAL2 [R/W] 00000000 ISBA2 [R/W] - 0000000 Reserved ITBAL3 [R/W] 00000000 ISBA3 [R/W] - 0000000 Reserved PCNL15 [R/W] 000000 - 0
Block
PPG 15
Reserved
I2C 2
I2C 3
Reserved
Reserved
Reserved
ROM Select Register
Reserved BSD0 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BSD1 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BSDC [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BSRR [R] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX Reserved
Reserved
Bit Search Module
Reserved (Continued)
52
DS07-16612-2E
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(Continued) Address 000440H 000444H 000448H 00044CH 000450H 000454H 000458H 00045CH 000460H 000464H 000468H 00046CH 000470H 000474H 000478H 00047CH 000480H 000484H 000488H Register +0 ICR00 [R/W] ---11111 ICR04 [R/W] ---11111 ICR08 [R/W] ---11111 ICR12 [R/W] ---11111 ICR16 [R/W] ---11111 ICR20 [R/W] ---11111 ICR24 [R/W] ---11111 ICR28 [R/W] ---11111 ICR32 [R/W] ---11111 ICR36 [R/W] ---11111 ICR40 [R/W] ---11111 ICR44 [R/W] ---11111 ICR48 [R/W] ---11111 ICR52 [R/W] ---11111 ICR56 [R/W] ---11111 ICR60 [R/W] ---11111 RSRR [R/W] 10000000 CLKR [R/W] ---- 0000 +1 ICR01 [R/W] ---11111 ICR05 [R/W] ---11111 ICR09 [R/W] ---11111 ICR13 [R/W] ---11111 ICR17 [R/W] ---11111 ICR21 [R/W] ---11111 ICR25 [R/W] ---11111 ICR29 [R/W] ---11111 ICR33 [R/W] ---11111 ICR37 [R/W] ---11111 ICR41 [R/W] ---11111 ICR45 [R/W] ---11111 ICR49 [R/W] ---11111 ICR53 [R/W] ---11111 ICR57 [R/W] ---11111 ICR61 [R/W] ---11111 STCR [R/W] 00110011 WPR [W] XXXXXXXX +2 ICR02 [R/W] ---11111 ICR06 [R/W] ---11111 ICR10 [R/W] ---11111 ICR14 [R/W] ---11111 ICR18 [R/W] ---11111 ICR22 [R/W] ---11111 ICR26 [R/W] ---11111 ICR30 [R/W] ---11111 ICR34 [R/W] ---11111 ICR38 [R/W] ---11111 ICR42 [R/W] ---11111 ICR46 [R/W] ---11111 ICR50 [R/W] ---11111 ICR54 [R/W] ---11111 ICR58 [R/W] ---11111 ICR62 [R/W] ---11111 TBCR [R/W] 00XXX - 00 DIVR0 [R/W] 00000011 +3 ICR03 [R/W] ---11111 ICR07 [R/W] ---11111 ICR11 [R/W] ---11111 ICR15 [R/W] ---11111 ICR19 [R/W] ---11111 ICR23 [R/W] ---11111 ICR27 [R/W] ---11111 ICR31 [R/W] ---11111 ICR35 [R/W] ---11111 ICR39 [R/W] ---11111 ICR43 [R/W] ---11111 ICR47 [R/W] ---11111 ICR51 [R/W] ---11111 ICR55 [R/W] ---11111 ICR59 [R/W] ---11111 ICR63 [R/W] ---11111 CTBR [W] XXXXXXXX DIVR1 [R/W] 00000000 Clock Control Reserved (Continued) Interrupt Controller Block
Reserved
DS07-16612-2E
53
MB91460D Series
(Continued) Address 00048CH 000490H Register +0 PLLDIVM [R/W] - - - - 0000 PLLCTRL [R/W] - - - - 0000 OSCC1 [R/W] - - - - - 010 PORTEN [R/W] - - - - - - 00 WTCER [R/W] - - - - - - 00 OSCS1 [R/W] 00001111 +1 PLLDIVN [R/W] - - 000000 +2 PLLDIVG [R/W] - - - - 0000 Reserved OSCC2 [R/W] - - - - - 010 Reserved Reserved Reserved Reserved WTHR [R/W] - - - 00000 CSVTR [R/W] - - - 00010 WTCR [R/W] 00000000 000 - 00 - 0 Real Time Clock (Watch Timer) OSCS2 [R/W] 00001111 Main/Sub Oscillator Control Port Input Enable Control Reserved +3 PLLMULG [W] 00000000 Block
PLL Interface
000494H
000498H 00049CH 0004A0H 0004A4H 0004A8H
WTBR [R/W] - - - XXXXX XXXXXXXX XXXXXXXX WTMR [R/W] - - 000000 CSVCR [R/W] 00011100 WTSR [R/W] - - 000000 CSCFG [R/W] 0X000000 Reserved CMCFG [R/W] 00000000
0004ACH
ClockSupervisor / Selector / Monitor Calibration of Sub Clock
0004B0H 0004B4H 0004B8H 0004BCH 0004C0H 0004C4H 0004C8H
CUCR [R/W] - - - - - - - - - - - 0 - - 00 CUTR1 [R] - - - - - - - - 00000000 CMPR [R/W] - - 000010 11111101 CMT1 [R/W] 00000000 1 - - - 0000 CANPRE [R/W] 0 - - - 0000 LVSEL [R/W] 00000111 OSCRH [R/W] 000 - - 001 OSCCR [R/W] -------0 CANCKD [R/W] - - - - - 000*1 LVDET [R/W] 0000 0 - 00 OSCRL [R/W] - - - - - 000
CUTD [R/W] 10000000 00000000 CUTR2 [R] 00000000 00000000 Reserved CMCR [R/W] - 001 - - 00
CMT2 [R/W] - - 000000 - - 000000 Reserved HWWDE [R/W] - - - - - - 00 WPCRH [R/W] 00 - - - 000 REGSEL [R/W] - - 000100
Clock Modulator
CAN Clock Control
HWWD [R/W, W] Low Voltage Detection/ 00011000 Hardware Watchdog WPCRL [R/W] - - - - - - 00 REGCTR [R/W] - - - 0 - - 00 Main-/Sub-Oscillation Stabilisation Timer Main- Oscillation Standby Control Main-/Sub regulator Control Reserved (Continued)
0004CCH
Reserved
0004D0H to 00063CH
Reserved
54
DS07-16612-2E
MB91460D Series
(Continued) Address 000640H 000644H 000648H 00064CH 000650H 000654H 000658H 00065CH 000660H 000664H 000668H 00066CH 000670H 000674H 000678H 00067CH 000680H 000684H 000688H to 0007F8H 0007FCH Reserved CSER [R/W] 00000001 RCRH [R/W] 00XXXXXX IORW0 [R/W] XXXXXXXX Register +0 +1 +2 +3 ASR0 [R/W] 00000000 00000000 ASR1 [R/W] XXXXXXXX XXXXXXXX ASR2 [R/W] XXXXXXXX XXXXXXXX ASR3 [R/W] XXXXXXXX XXXXXXXX ASR4 [R/W] XXXXXXXX XXXXXXXX ASR5 [R/W] XXXXXXXX XXXXXXXX ASR6 [R/W] XXXXXXXX XXXXXXXX ASR7 [R/W] XXXXXXXX XXXXXXXX AWR0 [R/W] 01001111 11111011 AWR2 [R/W] XXXXXXXX XXXXXXXX AWR4 [R/W] XXXXXXXX XXXXXXXX AWR6 [R/W] XXXXXXXX XXXXXXXX MCRA [R/W] XXXXXXXX MCRB [R/W] XXXXXXXX Reserved IORW1 [R/W] XXXXXXXX CHER [R/W] 11111111 RCRL [R/W] XXXX0XXX Reserved MODR [W] XXXXXXXX IORW2 [R/W] XXXXXXXX Reserved ACR0 [R/W] 1111**00 00100000*2 ACR1 [R/W] XXXXXXXX XXXXXXXX ACR2 [R/W] XXXXXXXX XXXXXXXX ACR3 [R/W] XXXXXXXX XXXXXXXX ACR4 [R/W] XXXXXXXX XXXXXXXX ACR5 [R/W] XXXXXXXX XXXXXXXX ACR6 [R/W] XXXXXXXX XXXXXXXX ACR7 [R/W] XXXXXXXX XXXXXXXX AWR1 [R/W] XXXXXXXX XXXXXXXX AWR3 [R/W] XXXXXXXX XXXXXXXX AWR5 [R/W] XXXXXXXX XXXXXXXX AWR7 [R/W] XXXXXXXX XXXXXXXX Reserved External Bus Block
Reserved Reserved TCR [R/W] 0000**** *3
Reserved
Reserved
Mode Register (Continued)
DS07-16612-2E
55
MB91460D Series
(Continued) Address 000800H to 000CFCH 000D00H 000D04H 000D08H 000D0CH 000D10H 000D14H 000D18H 000D1CH 000D20H to 000D3CH 000D40H 000D44H 000D48H 000D4CH 000D50H 000D54H 000D58H 000D5CH 000D60H to 000D7CH DDR00 [R/W] 00000000 DDR04 [R/W] - - - - - - 00 DDR08 [R/W] 00000000 Reserved DDR16 [R/W] 00000000 DDR20 [R/W] - - - - - 000 DDR24 [R/W] 00000000 Reserved PDRD00 [R] XXXXXXXX PDRD04 [R] - - - - - - XX PDRD08 [R] XXXXXXXX Reserved PDRD16 [R] XXXXXXXX PDRD20 [R] - - - - - XXX PDRD24 [R] XXXXXXXX Reserved Register +0 +1 Reserved PDRD01 [R] XXXXXXXX PDRD05 [R] XXXXXXXX PDRD09 [R] XX - - XXXX PDRD13 [R] - - - - - XXX PDRD17 [R] XXXX - - - Reserved PDRD25 [R] XXXXXXXX PDRD29 [R] XXXXXXXX Reserved DDR01 [R/W] 00000000 DDR05 [R/W] 00000000 DDR09 [R/W] 00 - - 0000 DDR13 [R/W] - - - - - 000 DDR17 [R/W] 0000 - - - Reserved DDR25 [R/W] 00000000 DDR29 [R/W] 00000000 Reserved DDR02 [R/W] 00000000 DDR06 [R/W] 00000000 DDR10 [R/W] - 000000 DDR14 [R/W] 00000000 DDR18 [R/W] - 000 - 000 DDR22 [R/W] - - 00 - 0 - 0 DDR26 [R/W] 00000000 DDR03 [R/W] 00000000 DDR07 [R/W] 00000000 Reserved DDR15 [R/W] - - - - 0000 DDR19 [R/W] - 000 - 000 DDR23 [R/W] - - 000000 DDR27 [R/W] 00000000 R-bus Port Direction Register PDRD02 [R] XXXXXXXX PDRD06 [R] XXXXXXXX PDRD10 [R] - XXXXXX PDRD14 [R] XXXXXXXX PDRD18 [R] - XXX - XXX PDRD22 [R] - - XX - X - X PDRD26 [R] XXXXXXXX PDRD03 [R] XXXXXXXX PDRD07 [R] XXXXXXXX Reserved PDRD15 [R] - - - - XXXX PDRD19 [R] - XXX - XXX PDRD23 [R] - - XXXXXX PDRD27 [R] XXXXXXXX R-bus Port Data Direct Read Register +2 +3 Block
Reserved
Reserved
Reserved
Reserved
Reserved (Continued)
56
DS07-16612-2E
MB91460D Series
(Continued) Address 000D80H 000D84H 000D88H 000D8CH 000D90H 000D94H 000D98H 000D9CH 000DA0H to 000DBCH 000DC0H 000DC4H 000DC8H 000DCCH 000DD0H 000DD4H 000DD8H 000DDCH 000DE0H to 000DFCH EPFR00 [R/W] -------EPFR04 [R/W] -------EPFR08 [R/W] -------Reserved EPFR16 [R/W] 0000 - - - EPFR20 [R/W] - - - - - 00 EPFR24 [R/W] -------Reserved Register +0 PFR00 [R/W] 11111111 PFR04 [R/W] - - - - - - 11 PFR08 [R/W] 11111111 Reserved PFR16 [R/W] 00000000 PFR20 [R/W] - - - - - 000 PFR24 [R/W] 00000000 Reserved +1 PFR01 [R/W] 11111111 PFR05 [R/W] 11111111 PFR09 [R/W] 11 - - 1111 PFR13 [R/W] - - - - - 000 PFR17 [R/W] 0000 - - - Reserved PFR25 [R/W] 00000000 PFR29 [R/W] 00000000 Reserved EPFR01 [R/W] -------EPFR05 [R/W] -------EPFR09 [R/W] -------EPFR13 [R/W] -----0-EPFR17 [R/W] -------Reserved EPFR25 [R/W] -------EPFR29 [R/W] -------Reserved EPFR02 [R/W] -------EPFR06 [R/W] -------EPFR10 [R/W] - - 00 - - - EPFR14 [R/W] 00000000 EPFR18 [R/W] - 00 - - 00 EPFR22 [R/W] -------EPFR26 [R/W] 00000000 EPFR03 [R/W] -------EPFR07 [R/W] -------Reserved EPFR15 [R/W] - - - - 0000 EPFR19 [R/W] -0---0-EPFR23 [R/W] -------EPFR27 [R/W] 00000000 R-bus Extra Port Function Register +2 PFR02 [R/W] 11111111 PFR06 [R/W] 11111111 PFR10 [R/W] - 111111 PFR14 [R/W] 00000000 PFR18 [R/W] - 000 - 000 PFR22 [R/W] - - 00 - 0 - 0 PFR26 [R/W] 00000000 +3 PFR03 [R/W] 11111111 PFR07 [R/W] 11111111 Reserved PFR15 [R/W] - - - - 0000 PFR19 [R/W] - 000 - 000 PFR23 [R/W] - - 000000 PFR27 [R/W] 00000000 R-bus Port Function Register Block
Reserved
Reserved
Reserved
Reserved (Continued)
DS07-16612-2E
57
MB91460D Series
(Continued) Address 000E00H 000E04H 000E08H 000E0CH 000E10H 000E14H 000E18H 000E1CH 000E20H to 000E3CH 000E40H 000E44H 000E48H 000E4CH 000E50H 000E54H 000E58H 000E5CH 000E60H to 000E7CH PILR00 [R/W] 00000000 PILR04 [R/W] - - - - - - 00 PILR08 [R/W] 00000000 Reserved PILR16 [R/W] 00000000 PILR20 [R/W] - - - - - 000 PILR24 [R/W] 00000000 Reserved Register +0 PODR00 [R/W] 00000000 PODR04 [R/W] - - - - - - 00 PODR08 [R/W] 00000000 Reserved PODR16 [R/W] 00000000 PODR20 [R/W] - - - - - 000 PODR24 [R/W] 00000000 Reserved +1 PODR01 [R/W] 00000000 PODR05 [R/W] 00000000 PODR09 [R/W] 00 - - 0000 PODR13 [R/W] - - - - - 000 PODR17 [R/W] 0000 - - - Reserved PODR25 [R/W] 00000000 PODR29 [R/W] 00000000 Reserved PILR01 [R/W] 00000000 PILR05 [R/W] 00000000 PILR09 [R/W] 00 - - 0000 PILR13 [R/W] - - - - - 000 PILR17 [R/W] 0000 - - - Reserved PILR25 [R/W] 00000000 PILR29 [R/W] 00000000 Reserved PILR02 [R/W] 00000000 PILR06 [R/W] 00000000 PILR10 [R/W] - 000000 PILR14 [R/W] 00000000 PILR18 [R/W] - 000 - 000 PILR22 [R/W] - - 00 - 0 - 0 PILR26 [R/W] 00000000 PILR03 [R/W] 00000000 PILR07 [R/W] 00000000 Reserved PILR15 [R/W] - - - - 0000 PILR19 [R/W] - 000 - 000 PILR23 [R/W] - - 000000 PILR27 [R/W] 00000000 R-bus Port Input Level Select Register +2 PODR02 [R/W] 00000000 PODR06 [R/W] 00000000 PODR10 [R/W] - 000000 PODR14 [R/W] 00000000 PODR18 [R/W] - 000 - 000 PODR22 [R/W] - - 00 - 0 - 0 PODR26 [R/W] 00000000 +3 PODR03 [R/W] 00000000 PODR07 [R/W] 00000000 Reserved PODR15 [R/W] - - - - 0000 PODR19 [R/W] - 000 - 000 PODR23 [R/W] - - 000000 PODR27 [R/W] 00000000 R-bus Port Output Drive Select Register Block
Reserved
Reserved
Reserved
Reserved (Continued)
58
DS07-16612-2E
MB91460D Series
(Continued) Address 000E80H 000E84H 000E88H 000E8CH 000E90H 000E94H 000E98H 000E9CH 000EA0H to 000EBCH 000EC0H 000EC4H 000EC8H 000ECCH 000ED0H 000ED4H 000ED8H 000EDCH 000EE0H to 000EFCH PPER00 [R/W] 00000000 PPER04 [R/W] - - - - - - 00 PPER08 [R/W] 00000000 Reserved PPER16 [R/W] 00000000 PPER20 [R/W] - - - - - 000 PPER24 [R/W] 00000000 Reserved Register +0 EPILR00 [R/W] 00000000 EPILR04 [R/W] - - - - - - 00 EPILR08 [R/W] 00000000 Reserved EPILR16 [R/W] 00000000 EPILR20 [R/W] - - - - - 000 EPILR24 [R/W] 00000000 Reserved +1 EPILR01 [R/W] 00000000 EPILR05 [R/W] 00000000 EPILR09 [R/W] 00 - - 0000 EPILR13 [R/W] - - - - - 000 EPILR17 [R/W] 0000 - - - Reserved EPILR25 [R/W] 00000000 EPILR29 [R/W] 00000000 Reserved PPER01 [R/W] 00000000 PPER05 [R/W] 00000000 PPER09 [R/W] 00 - - 0000 PPER13 [R/W] - - - - - 000 PPER17 [R/W] 0000 - - - Reserved PPER25 [R/W] 00000000 PPER29 [R/W] 00000000 Reserved PPER02 [R/W] 00000000 PPER06 [R/W] 00000000 PPER10 [R/W] - 000000 PPER14 [R/W] 00000000 PPER18 [R/W] - 000 - 000 PPER22 [R/W] - - 00 - 0 - 0 PPER26 [R/W] 00000000 PPER03 [R/W] 00000000 PPER07 [R/W] 00000000 Reserved PPER15 [R/W] - - - - 0000 PPER19 [R/W] - 000 - 000 PPER23 [R/W] - - 000000 PPER27 [R/W] 00000000 R-bus Port Pull-Up/Down Enable Register +2 EPILR02 [R/W] 00000000 EPILR06 [R/W] 00000000 EPILR10 [R/W] - 000000 EPILR14 [R/W] 00000000 EPILR18 [R/W] - 000 - 000 EPILR22 [R/W] - - 00 - 0 - 0 EPILR26 [R/W] 00000000 +3 EPILR03 [R/W] 00000000 EPILR07 [R/W] 00000000 Reserved EPILR15 [R/W] - - - - 0000 EPILR19 [R/W] - 000 - 000 EPILR23 [R/W] - - 000000 EPILR27 [R/W] 00000000 R-bus Extra Port Input Level Select Register Block
Reserved
Reserved
Reserved
Reserved (Continued)
DS07-16612-2E
59
MB91460D Series
(Continued) Address 000F00H 000F04H 000F08H 000F0CH 000F10H 000F14H 000F18H 000F1CH 000F20H to 000F3CH 001000H 001004H 001008H 00100CH 001010H 001014H 001018H 00101CH 001020H 001024H 001028H to 001FFCH Register +0 PPCR00 [R/W] 11111111 PPCR04 [R/W] - - - - - - 11 PPCR08 [R/W] 11111111 Reserved PPCR16 [R/W] 11111111 PPCR20 [R/W] - - - - - 111 PPCR24 [R/W] 11111111 Reserved +1 PPCR01 [R/W] 11111111 PPCR05 [R/W] 11111111 PPCR09 [R/W] 11 - - 1111 PPCR13 [R/W] - - - - - 111 PPCR17 [R/W] 1111 - - - Reserved PPCR25 [R/W] 11111111 PPCR29 [R/W] 11111111 Reserved DMASA0 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMADA0 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMASA1 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMADA1 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMASA2 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMADA2 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMASA3 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMADA3 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMASA4 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMADA4 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX Reserved Reserved (Continued) 60 DS07-16612-2E +2 PPCR02 [R/W] 11111111 PPCR06 [R/W] 11111111 PPCR10 [R/W] - 111111 PPCR14 [R/W] 11111111 PPCR18 [R/W] - 111 - 111 PPCR22 [R/W] - - 11 - 1 - 1 PPCR26 [R/W] 11111111 +3 PPCR03 [R/W] 11111111 PPCR07 [R/W] 11111111 Reserved PPCR15 [R/W] - - - - 1111 PPCR19 [R/W] - 111 - 111 PPCR23 [R/W] - - 111111 PPCR27 [R/W] 11111111 R-bus Port Pull-Up/Down Control Register Block
Reserved
Reserved
DMAC
MB91460D Series
(Continued) Address 002000H to 006FFCH 007000H 007004H 007008H 00700CH 007010H 007014H to 007FFCH 008000H to 00BFFCH 00C000H 00C004H 00C008H 00C00CH 00C010H 00C014H 00C018H 00C01CH Register +0 +1 +2 +3 Block Flash-cache / I-RAM area
MB91F467Dx Flash-cache size is 8 Kbytes : 004000H to 005FFCH MB91F465DA Flash-cache size is 8 Kbytes : 004000H to 005FFCH FMCS [R/W] 01101000 FMCR [R] - - - 00000 FCHCR [R/W] - - - - - - 00 10000011 FMWT2 [R] - 001 - - - FMPS [R/W] - - - - - 000
FMWT [R/W] 11111111 11111111
FMAC [R] 00000000 00000000 00000000 00000000 FCHA0 [R/W] - - - - - - - - - - - 00000 00000000 00000000 FCHA1 [R/W] - - - - - - - - - - - 00000 00000000 00000000 Reserved MB91F467Dx Boot-ROM size is 4 Kbytes : 00B000H to 00BFFCH MB91F465DA Boot-ROM size is 4 Kbytes : 00B000H to 00BFFCH (instruction access is 1 wait cycle, data access is 1 wait cycle) CTRLR0 [R/W] 00000000 00000001 ERRCNT0 [R] 00000000 00000000 INTR0 [R] 00000000 00000000 BRPE0 [R/W] 00000000 00000000 IF1CREQ0 [R/W] 00000000 00000001 IF1MSK20 [R/W] 11111111 11111111 IF1ARB20 [R/W] 00000000 00000000 IF1MCTR0 [R/W] 00000000 00000000 STATR0 [R/W] 00000000 00000000 BTR0 [R/W] 00100011 00000001 TESTR0 [R/W] 00000000 X0000000 Reserved IF1CMSK0 [R/W] 00000000 00000000 IF1MSK10 [R/W] 11111111 11111111 IF1ARB10 [R/W] 00000000 00000000 Reserved
Flash Memory/ Flash-cache/ I-RAM Control Register
Flash-cache Noncacheable area setting Register
Reserved
Boot ROM area
CAN 0 Control Register
CAN 0 IF 1 Register
(Continued)
DS07-16612-2E
61
MB91460D Series
(Continued) Address 00C020H 00C024H 00C028H, 00C02CH 00C030H 00C034H 00C038H, 00C03CH 00C040H 00C044H 00C048H 00C04CH 00C050H 00C054H 00C058H, 00C05CH 00C060H 00C064H 00C068H to 00C07CH IF2DTA20 [R/W] 00000000 00000000 IF2DTB20 [R/W] 00000000 00000000 Reserved (Continued) IF2CREQ0 [R/W] 00000000 00000001 IF2MSK20 [R/W] 11111111 11111111 IF2ARB20 [R/W] 00000000 00000000 IF2MCTR0 [R/W] 00000000 00000000 IF2DTA10 [R/W] 00000000 00000000 IF2DTB10 [R/W] 00000000 00000000 Reserved IF2DTA10 [R/W] 00000000 00000000 IF2DTB10 [R/W] 00000000 00000000 IF1DTA20 [R/W] 00000000 00000000 IF1DTB20 [R/W] 00000000 00000000 Reserved IF2CMSK0 [R/W] 00000000 00000000 IF2MSK10 [R/W] 11111111 11111111 IF2ARB10 [R/W] 00000000 00000000 Reserved IF2DTA20 [R/W] 00000000 00000000 IF2DTB20 [R/W] 00000000 00000000 Register +0 +1 +2 +3 IF1DTA10 [R/W] 00000000 00000000 IF1DTB10 [R/W] 00000000 00000000 Reserved IF1DTA10 [R/W] 00000000 00000000 IF1DTB10 [R/W] 00000000 00000000 IF1DTA20 [R/W] 00000000 00000000 IF1DTB20 [R/W] 00000000 00000000 CAN 0 IF 1 Register Block
CAN 0 IF 2 Register
62
DS07-16612-2E
MB91460D Series
(Continued) Address 00C080H 00C084H to 00C08CH 00C090H 00C094H to 00C09CH 00C0A0H 00C0A4H to 00C0ACH 00C0B0H 00C0B4H to 00C0FCH 00C100H 00C104H 00C108H 00C10CH 00C110H 00C114H 00C118H 00C11CH 00C120H 00C124H CTRLR1 [R/W] 00000000 00000001 ERRCNT1 [R] 00000000 00000000 INTR1 [R] 00000000 00000000 BRPE1 [R/W] 00000000 00000000 IF1CREQ1 [R/W] 00000000 00000001 IF1MSK21 [R/W] 11111111 11111111 IF1ARB21 [R/W] 00000000 00000000 IF1MCTR1 [R/W] 00000000 00000000 IF1DTA11 [R/W] 00000000 00000000 IF1DTB11 [R/W] 00000000 00000000 MSGVAL20 [R] 00000000 00000000 Reserved STATR1 [R/W] 00000000 00000000 BTR1 [R/W] 00100011 00000001 TESTR1 [R/W] 00000000 X0000000 Reserved IF1CMSK1 [R/W] 00000000 00000000 IF1MSK11 [R/W] 11111111 11111111 IF1ARB11 [R/W] 00000000 00000000 Reserved IF1DTA21 [R/W] 00000000 00000000 IF1DTB21 [R/W] 00000000 00000000 (Continued) CAN 1 IF 1 Register CAN 1 Control Register INTPND20 [R] 00000000 00000000 Reserved MSGVAL10 [R] 00000000 00000000 Reserved NEWDT20 [R] 00000000 00000000 Reserved INTPND10 [R] 00000000 00000000 Register +0 +1 +2 +3 TREQR20 [R] 00000000 00000000 Reserved NEWDT10 [R] 00000000 00000000 CAN 0 Status Flags TREQR10 [R] 00000000 00000000 Block
DS07-16612-2E
63
MB91460D Series
(Continued) Address 00C128H, 00C12CH 00C130H 00C134H 00C138H, 00C13CH 00C140H 00C144H 00C148H 00C14CH 00C150H 00C154H 00C158H, 00C15CH 00C160H 00C164H 00C168H to 00C17CH 00C180H 00C184H to 00C18CH 00C190H 00C194H to 00C19CH NEWDT21 [R] 00000000 00000000 Reserved (Continued) TREQR21 [R] 00000000 00000000 Reserved NEWDT11 [R] 00000000 00000000 CAN 1 Status Flags IF2DTA21 [R/W] 00000000 00000000 IF2DTB21 [R/W] 00000000 00000000 Reserved TREQR11 [R] 00000000 00000000 IF2CREQ1 [R/W] 00000000 00000001 IF2MSK21 [R/W] 11111111 11111111 IF2ARB21 [R/W] 00000000 00000000 IF2MCTR1 [R/W] 00000000 00000000 IF2DTA11 [R/W] 00000000 00000000 IF2DTB11 [R/W] 00000000 00000000 Reserved IF2DTA11 [R/W] 00000000 00000000 IF2DTB11 [R/W] 00000000 00000000 IF1DTA21 [R/W] 00000000 00000000 IF1DTB21 [R/W] 00000000 00000000 Reserved IF2CMSK1 [R/W] 00000000 00000000 IF2MSK11 [R/W] 11111111 11111111 IF2ARB11 [R/W] 00000000 00000000 Reserved IF2DTA21 [R/W] 00000000 00000000 IF2DTB21 [R/W] 00000000 00000000 Register +0 +1 Reserved IF1DTA11 [R/W] 00000000 00000000 IF1DTB11 [R/W] 00000000 00000000 +2 +3 Block
CAN 1 IF 1 Register
CAN 1 IF 2 Register
64
DS07-16612-2E
MB91460D Series
(Continued) Address 00C1A0H 00C1A4H to 00C1ACH 00C1B0H 00C1B4H to 00C1FCH 00C200H 00C204H 00C208H 00C20CH 00C210H 00C214H 00C218H 00C21CH 00C220H 00C224H 00C228H, 00C22CH 00C230H 00C234H 00C238H, 00C23CH IF1DTA22 [R/W] 00000000 00000000 IF1DTB22 [R/W] 00000000 00000000 Reserved (Continued) CTRLR2 [R/W] 00000000 00000001 ERRCNT2 [R] 00000000 00000000 INTR2 [R] 00000000 00000000 BRPE2 [R/W] 00000000 00000000 IF1CREQ2 [R/W] 00000000 00000001 IF1MSK22 [R/W] 11111111 11111111 IF1ARB22 [R/W] 00000000 00000000 IF1MCTR2 [R/W] 00000000 00000000 IF1DTA12 [R/W] 00000000 00000000 IF1DTB12 [R/W] 00000000 00000000 Reserved IF1DTA12 [R/W] 00000000 00000000 IF1DTB12 [R/W] 00000000 00000000 MSGVAL21 [R] 00000000 00000000 Reserved STATR2 [R/W] 00000000 00000000 BTR2 [R/W] 00100011 00000001 TESTR2 [R/W] 00000000 X0000000 Reserved IF1CMSK2 [R/W] 00000000 00000000 IF1MSK12 [R/W] 11111111 11111111 IF1ARB12 [R/W] 00000000 00000000 Reserved IF1DTA22 [R/W] 00000000 00000000 IF1DTB22 [R/W] 00000000 00000000 CAN 2 Control Register Register +0 +1 +2 +3 INTPND21 [R] 00000000 00000000 Reserved MSGVAL11 [R] 00000000 00000000 CAN 1 Status Flags INTPND11 [R] 00000000 00000000 Block
CAN 2 IF 1 Register
DS07-16612-2E
65
MB91460D Series
(Continued) Address 00C240H 00C244H 00C248H 00C24CH 00C250H 00C254H 00C258H, 00C25CH 00C260H 00C264H 00C268H to 00C27CH 00C280H 00C284H to 00C28CH 00C290H 00C294H to 00C29CH 00C2A0H 00C2A4H to 00C2ACH 00C2B0H MSGVAL22 [R] 00000000 00000000 INTPND22 [R] 00000000 00000000 Reserved MSGVAL12 [R] 00000000 00000000 (Continued) NEWDT22 [R] 00000000 00000000 Reserved INTPND12 [R] 00000000 00000000 TREQR22 [R] 00000000 00000000 Reserved NEWDT12 [R] 00000000 00000000 CAN 2 Status Flags IF2DTA22 [R/W] 00000000 00000000 IF2DTB22 [R/W] 00000000 00000000 Reserved TREQR12 [R] 00000000 00000000 Register +0 +1 +2 +3 IF2CREQ2 [R/W] 00000000 00000001 IF2MSK22 [R/W] 11111111 11111111 IF2ARB22 [R/W] 00000000 00000000 IF2MCTR2 [R/W] 00000000 00000000 IF2DTA12 [R/W] 00000000 00000000 IF2DTB12 [R/W] 00000000 00000000 Reserved IF2DTA12 [R/W] 00000000 00000000 IF2DTB12 [R/W] 00000000 00000000 IF2CMSK2 [R/W] 00000000 00000000 IF2MSK12 [R/W] 11111111 11111111 IF2ARB12 [R/W] 00000000 00000000 Reserved IF2DTA22 [R/W] 00000000 00000000 IF2DTB22 [R/W] 00000000 00000000 Block
CAN 2 IF 2 Register
66
DS07-16612-2E
MB91460D Series
(Continued) Address 00C2B4H to 00EFFCH 00F000H 00F004H 00F008H 00F00CH 00F010H 00F014H to 00F01CH 00F020H 00F024H 00F028H 00F02CH 00F030H to 00F07CH 00F080H 00F084H 00F088H 00F08CH 00F090H 00F094H 00F098H Register +0 +1 Reserved BCTRL [R/W] - - - - - - - - - - - - - - - - 11111100 00000000 BSTAT [R/W] - - - - - - - - - - - - - 000 00000000 10 - - 0000 BIAC [R] - - - - - - - - - - - - - - - - 00000000 00000000 BOAC [R] - - - - - - - - - - - - - - - - 00000000 00000000 BIRQ [R/W] - - - - - - - - - - - - - - - - 00000000 00000000 EDSU / MPU Reserved BCR0 [R/W] - - - - - - - - 00000000 00000000 00000000 BCR1 [R/W] - - - - - - - - 00000000 00000000 00000000 BCR2 [R/W] - - - - - - - - 00000000 00000000 00000000 BCR3 [R/W] - - - - - - - - 00000000 00000000 00000000 Reserved BAD0 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BAD1 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BAD2 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BAD3 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BAD4 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BAD5 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BAD6 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX (Continued) DS07-16612-2E 67 EDSU / MPU Reserved +2 +3 Block
Reserved
MB91460D Series
Address 00F09CH 00F0A0H 00F0A4H 00F0A8H 00F0ACH 00F0B0H 00F0B4H 00F0B8H 00F0BCH 00F0C0H to 01FFFCH 020000H to 02FFFCH 030000H to 03FFFCH
Register +0 +1 +2 +3 BAD7 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BAD8 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BAD9 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BAD10 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BAD11 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BAD12 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BAD13 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BAD14 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BAD15 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX Reserved MB91F467Dx D-RAM size is 32 Kbytes : 028000H to 02FFFCH MB91F465DA D-RAM size is 32 Kbytes : 028000H to 02FFFCH (data access is 0 wait cycles) MB91F467Dx ID-RAM size is 32 Kbytes : 030000H to 037FFCH MB91F465DA ID-RAM size is 16 Kbytes : 030000H to 033FFCH (instruction access is 0 wait cycles, data access is 1 wait cycle)
Block
EDSU / MPU
Reserved
D-RAM area
ID-RAM area
*1 : depends on the number of available CAN channels *2 : ACR0 [11 : 10] depends on bus width setting in Mode vector fetch information *3 : TCR [3 : 0] INIT value = 0000, keeps value after RST
68
DS07-16612-2E
MB91460D Series
2. Flash memory and external bus area
dat[31:0] dat[31:16] +0 +1 dat[15:0] +2 +3 dat[31:16] Register +4 +5 +6 +7 dat[31:0] dat[15:0] Block
32bit read/write 16bit read/write Address 040000H to 05FFF8H 060000H to 07FFF8H 080000H to 09FFF8H 0A0000H to 0BFFF8H 0C0000H to 0DFFF8H 0E0000H to 0FFFF0H 0FFFF8H 100000H to 11FFF8H 120000H to 13FFF8H 140000H to 143FF8H 144000H to 147FF8H 148000H to 14BFF8H 14C000H to 14FFF8H 150000H to 17FFF8H DS07-16612-2E
SA8 (64KB, MB91F467Dx) External bus (MB91F465DA) SA10 (64KB, MB91F467Dx) External bus (MB91F465DA)
SA9 (64KB, MB91F467Dx) External bus (MB91F465DA) SA11 (64KB, MB91F467Dx) External bus (MB91F465DA)
ROMS0
ROMS1
SA12 (64KB)
SA13 (64KB)
ROMS2
SA14 (64KB)
SA15 (64KB)
ROMS3
SA16 (64KB)
SA17 (64KB)
ROMS4
SA18 (64KB) FMV [R] 06 00 00 00H SA20 (64KB, MB91F467Dx) External bus (MB91F465DA) SA22 (64KB, MB91F467Dx) External bus (MB91F465DA) SA0 (8KB, MB91F467Dx) Reserved (MB91F465DA) SA2 (8KB, MB91F467Dx) Reserved (MB91F465DA)
SA19 (64KB) ROMS5 FRV [R] 00 00 BF F8H SA21 (64KB, MB91F467Dx) External bus (MB91F465DA) ROMS6 SA23 (64KB, MB91F467Dx) External bus (MB91F465DA) SA1 (8KB, MB91F467Dx) Reserved (MB91F465DA) SA3 (8KB, MB91F467Dx) Reserved (MB91F465DA)
SA4 (8KB, MB91F467Dx)
SA5 (8KB, MB91F467Dx)
ROMS7
SA6 (8KB, MB91F467Dx)
SA7 (8KB, MB91F467Dx)
Reserved
69
MB91460D Series
32bit read/write 16bit read/write Address 180000H to 1BFFF8H 1C0000H to 1FFFF8H 200000H to 27FFF8H 280000H to 2FFFF8H 300000H to 37FFF8H 380000H to 3FFFF8H 400000H to 47FFF8H 480000H to 4FFFF8H dat[31:16] +0 +1 dat[31:0] dat[15:0] +2 +3 dat[31:16] Register +4 +5 +6 +7 dat[31:0] dat[15:0] Block
ROMS8
ROMS9
ROMS10
ROMS11 External Bus Area ROMS12
ROMS13
ROMS14
ROMS15
Notes: Write operations to address 0FFFF8H and 0FFFFCH are not possible. When reading these addresses, the values shown above will be read. On MB91F465DA, write access to the flash is only possible in 16-bit mode.
70
DS07-16612-2E
MB91460D Series
ELBA T RO C V PU NI
Interrupt Interrupt number
eciD l am eH ax deciml a
Interrupt level
*
etting S eiter R gs eiter R gs ddress a
1
Interrupt vector
et sf O eult ector D af V ddress a
*2
MA D eource Rs number
Reset Mode vector System reserved System reserved System reserved CPU supervisor mode (INT #5 instruction) *5 Memory Protection exception *5 System reserved System reserved System reserved System reserved System reserved System reserved System reserved Undefined instruction exception NMI request External Interrupt 0 External Interrupt 1 External Interrupt 2 External Interrupt 3 External Interrupt 4 External Interrupt 5 External Interrupt 6 External Interrupt 7 External Interrupt 8 External Interrupt 9 External Interrupt 10 System reserved External Interrupt 12 External Interrupt 13 External Interrupt 14 System reserved
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F
FH fixed ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07

3FCH 3F8H 3F4H 3F0H 3ECH 3E8H 3E4H 3E0H 3DCH 3D8H 3D4H 3D0H 3CCH 3C8H 3C4H 3C0H 3BCH 3B8H 3B4H 3B0H 3ACH 3A8H 3A4H 3A0H 39CH 398H 394H 390H 38CH 388H 384H 380H
000FFFFCH 000FFFF8H 000FFFF4H 000FFFF0H 000FFFECH 000FFFE8H 000FFFE4H 000FFFE0H 000FFFDCH 000FFFD8H 000FFFD4H 000FFFD0H 000FFFCCH 000FFFC8H 000FFFC4H 000FFFC0H 000FFFBCH 000FFFB8H 000FFFB4H 000FFFB0H 000FFFACH 000FFFA8H 000FFFA4H 000FFFA0H 000FFF9CH 000FFF98H 000FFF94H 000FFF90H 000FFF8CH 000FFF88H 000FFF84H 000FFF80H
0, 16 1, 17 2, 18 3, 19 20 21 22 23 (Continued)
440H 441H 442H 443H 444H 445H 446H 447H
DS07-16612-2E
71
MB91460D Series
Interrupt
Interrupt number
eciD l am eH ax deciml a
Interrupt level
etting S eiter R gs eiter R gs ddress a
*1
Interrupt vector
et sf O eult ector D af V ddress a
*2
MA D eource Rs number
Reload Timer 0 Reload Timer 1 Reload Timer 2 Reload Timer 3 Reload Timer 4 Reload Timer 5 Reload Timer 6 Reload Timer 7 Free Run Timer 0 Free Run Timer 1 Free Run Timer 2 Free Run Timer 3 Free Run Timer 4 Free Run Timer 5 Free Run Timer 6 Free Run Timer 7 CAN 0 CAN 1 CAN 2 System reserved System reserved System reserved System reserved System reserved System reserved System reserved LIN-USART 2 RX LIN-USART 2 TX System reserved System reserved System reserved Delayed Interrupt
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F
ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 ICR14 ICR15 ICR16 ICR17 ICR18 ICR19 ICR20 ICR21 ICR22 ICR23 *3
448H 449H 44AH 44BH 44CH 44DH 44EH 44FH 450H 451H 452H 453H 454H 455H 456H 457H
37CH 378H 374H 370H 36CH 368H 364H 360H 35CH 358H 354H 350H 34CH 348H 344H 340H 33CH 338H 334H 330H 32CH 328H 324H 320H 31CH 318H 314H 310H 30CH 308H 304H 300H
000FFF7CH 000FFF78H 000FFF74H 000FFF70H 000FFF6CH 000FFF68H 000FFF64H 000FFF60H 000FFF5CH 000FFF58H 000FFF54H 000FFF50H 000FFF4CH 000FFF48H 000FFF44H 000FFF40H 000FFF3CH 000FFF38H 000FFF34H 000FFF30H 000FFF2CH 000FFF28H 000FFF24H 000FFF20H 000FFF1CH 000FFF18H 000FFF14H 000FFF10H 000FFF0CH 000FFF08H 000FFF04H 000FFF00H
4, 32 5, 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 6, 48 7, 49 8, 50 9, 51 52 53 54 55 (Continued)
72
DS07-16612-2E
MB91460D Series
Interrupt
Interrupt number
eciD l am eH ax deciml a
Interrupt level
etting S eiter R gs eiter R gs ddress a
*1
Interrupt vector
et sf O eult ector D af V ddress a
*2
MA D eource Rs number
System reserved *4 System reserved *4 LIN-USART (FIFO) 4 RX LIN-USART (FIFO) 4 TX LIN-USART (FIFO) 5 RX LIN-USART (FIFO) 5 TX LIN-USART (FIFO) 6 RX LIN-USART (FIFO) 6 TX LIN-USART (FIFO) 7 RX LIN-USART (FIFO) 7 TX I2C 0 / I2C 2 IC3 System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved Input Capture 0 Input Capture 1 Input Capture 2 Input Capture 3
2
64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95
40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F
(ICR24) ICR25 ICR26 ICR27 ICR28 ICR29 ICR30 ICR31 ICR32 ICR33 ICR34 ICR35 ICR36 ICR37 ICR38 ICR39
(458H) 459H 45AH 45BH 45CH 45DH 45EH 45FH 460H 461H 462H 463H 464H 465H 466H 467H
2FCH 2F8H 2F4H 2F0H 2ECH 2E8H 2E4H 2E0H 2DCH 2D8H 2D4H 2D0H 2CCH 2C8H 2C4H 2C0H 2BCH 2B8H 2B4H 2B0H 2ACH 2A8H 2A4H 2A0H 29CH 298H 294H 290H 28CH 288H 284H 280H
000FFEFCH 000FFEF8H 000FFEF4H 000FFEF0H 000FFEECH 000FFEE8H 000FFEE4H 000FFEE0H 000FFEDCH 000FFED8H 000FFED4H 000FFED0H 000FFECCH 000FFEC8H 000FFEC4H 000FFEC0H 000FFEBCH 000FFEB8H 000FFEB4H 000FFEB0H 000FFEACH 000FFEA8H 000FFEA4H 000FFEA0H 000FFE9CH 000FFE98H 000FFE94H 000FFE90H 000FFE8CH 000FFE88H 000FFE84H 000FFE80H
10, 56 11, 57 12, 58 13, 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 (Continued)
DS07-16612-2E
73
MB91460D Series
Interrupt
Interrupt number
eciD l am eH ax deciml a
Interrupt level
etting S eiter R gs eiter R gs ddress a
*1
Interrupt vector
et sf O eult ector D af V ddress a
*2
MA D eource Rs number
Input Capture 4 Input Capture 5 Input Capture 6 Input Capture 7 Output Compare 0 Output Compare 1 Output Compare 2 Output Compare 3 System reserved System reserved System reserved System reserved Sound Generator Phase Frequency Modulator System reserved System reserved System reserved System reserved System reserved System reserved PPG4 PPG5 PPG6 PPG7 PPG8 PPG9 PPG10 PPG11 PPG12 PPG13 PPG14 PPG15
96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127
60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F
ICR40 ICR41 ICR42 ICR43 ICR44 ICR45 ICR46 ICR47 *3 ICR48 ICR49 ICR50 ICR51 ICR52 ICR53 ICR54 ICR55
468H 469H 46AH 46BH 46CH 46DH 46EH 46FH 470H 471H 472H 473H 474H 475H 476H 477H
27CH 278H 274H 270H 26CH 268H 264H 260H 25CH 258H 254H 250H 24CH 248H 244H 240H 23CH 238H 234H 230H 22CH 228H 224H 220H 21CH 218H 214H 210H 20CH 208H 204H 200H
000FFE7CH 000FFE78H 000FFE74H 000FFE70H 000FFE6CH 000FFE68H 000FFE64H 000FFE60H 000FFE5CH 000FFE58H 000FFE54H 000FFE50H 000FFE4CH 000FFE48H 000FFE44H 000FFE40H 000FFE3CH 000FFE38H 000FFE34H 000FFE30H 000FFE2CH 000FFE28H 000FFE24H 000FFE20H 000FFE1CH 000FFE18H 000FFE14H 000FFE10H 000FFE0CH 000FFE08H 000FFE04H 000FFE00H
84 85 86 87 88 89 90 91 92 93 94 95 15, 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 (Continued)
74
DS07-16612-2E
MB91460D Series
(Continued) Interrupt Interrupt number
Decimal Hexadecimal
Interrupt level
Setting Register
*1
Interrupt vector
Offset
*2
Register address
Default Vector address
DMA Resource number
Up/Down Counter 0 System reserved Up/Down Counter 2 Up/Down Counter 3 Real Time Clock Calibration Unit A/D Converter 0 System reserved Alarm Comparator 0 System reserved Low Voltage Detection SMC Comparator 0 to 5 Timebase Overflow PLL Clock Gear DMA Controller Main/Sub OSC stability wait Security vector Used by the INT instruction.
128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 to 255
80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 to FF
ICR56 ICR57 ICR58 ICR59 ICR60 ICR61 ICR62 ICR63
478H 479H 47AH 47BH 47CH 47DH 47EH 47FH
1FCH 1F8H 1F4H 1F0H 1ECH 1E8H 1E4H 1E0H 1DCH 1D8H 1D4H 1D0H 1CCH 1C8H 1C4H 1C0H 1BCH 1B8H to 000H
000FFDFCH 000FFDF8H 000FFDF4H 000FFDF0H 000FFDECH 000FFDE8H 000FFDE4H 000FFDE0H 000FFDDCH 000FFDD8H 000FFDD4H 000FFDD0H 000FFDCCH 000FFDC8H 000FFDC4H 000FFDC0H 000FFDBCH 000FFDB8H to 000FFC00H
14, 112
*1 : The Interrupt Control Registers (ICRs) are located in the interrupt controller and set the interrupt level for each interrupt request. An ICR is provided for each interrupt request. *2 : The vector address for each EIT (exception, interrupt or trap) is calculated by adding the listed offset to the table base register value (TBR) . The TBR specifies the top of the EIT vector table. The addresses listed in the table are for the default TBR value (000FFC00H) . The TBR is initialized to this value by a reset. The TBR is set to 000FFC00H after the internal boot ROM is executed. *3 : ICR23 and ICR47 can be exchanged by setting the REALOS compatibility bit (addr 0C03H : IOS[0]) *4 : Used by REALOS *5 : Memory Protection Unit (MPU) support
DS07-16612-2E
75
MB91460D Series
S G NDIET M O C R
1. PL aId Clockge r s t i
Please note that for MB91F467Dx the core base clock frequencies are valid in the 1.8V operation mode of the Main regulator and Flash. Recommended PLL divide r and clockgear settings PLL Input (CLK) [MHz] 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 Frequency Parameter DIVM 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 4 4 4 4 6 8 10 12 DIVN 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 Clockgear Parameter DIVG 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 MULG 24 24 24 24 20 20 20 20 16 16 16 16 12 12 12 24 24 24 24 24 28 32 32 200 192 184 176 168 160 152 144 136 128 120 112 104 96 88 160 144 128 112 144 160 160 144 PLL Output (X) [MHz] Core Base Clock [MHz] 100 96 92 88 84 80 76 72 68 64 60 56 52 48 44 40 36 32 28 24 20 16 12
Remarks
MULG
*1
*1 This setting is not possible at MB91F467Dx
76
DS07-16612-2E
MB91460D Series
2. Clock Modulator settings
The following table shows all possible settings for the Clock Modulator in a base clock frequency range from 32MHz up to 88MHz. The Flash access time settings need to be adjusted according to Fmax while the PLL and clockgear settings should be set according to base clock frequency. Clock Modulator settings, frequency Modulation Degree (k) 1 1 1 1 2 1 1 1 2 3 1 1 1 2 3 1 1 1 1 2 2 3 4 1 1 1 1 1 2 2 DS07-16612-2E Random No (N) 3 3 3 5 3 3 5 7 3 3 3 5 7 3 3 3 5 7 9 3 5 3 3 3 5 7 9 11 3 5 range and supported supply voltage CMPR [hex] 026F 026F 026F 02AE 046E 026F 02AE 02ED 046E 066D 026F 02AE 02ED 046E 066D 026F 02AE 02ED 032C 046E 04AC 066D 086C 026F 02AE 02ED 032C 036B 046E 04AC Baseclk [MHz] 88 84 80 80 80 76 76 76 76 76 72 72 72 72 72 68 68 68 68 68 68 68 68 64 64 64 64 64 64 64 Fmin [MHz] 79.5 76.1 72.6 68.7 68.7 69.1 65.3 62 65.3 62 65.5 62 58.8 62 58.8 62 58.7 55.7 53 58.7 53 55.7 53 58.5 55.3 52.5 49.9 47.6 55.3 49.9 Fmax [MHz] 98.5 93.8 89.1 95.8 95.8 84.5 90.8 98.1 90.8 98.1 79.9 85.8 92.7 85.8 92.7 75.3 80.9 87.3 95 80.9 95 87.3 95 70.7 75.9 82 89.1 97.6 75.9 89.1 77
*1 *1 *1
Remarks
*1
MB91460D Series
(Continued) (Continued) Modulation Degree (k) 3 4 5 1 1 1 1 1 2 2 3 4 5 1 1 1 1 1 1 2 2 2 3 3 4 5 6 1 1 1 1 1 1 1 2 Random No (N) 3 3 3 3 5 7 9 11 3 5 3 3 3 3 5 7 9 11 13 3 5 7 3 5 3 3 3 3 5 7 9 11 13 15 3 CMPR [hex] 066D 086C 0A6B 026F 02AE 02ED 032C 036B 046E 04AC 066D 086C 0A6B 026F 02AE 02ED 032C 036B 03AA 046E 04AC 04EA 066D 06AA 086C 0A6B 0C6A 026F 02AE 02ED 032C 036B 03AA 03E9 046E eclk saB M]zH [ 64 64 64 60 60 60 60 60 60 60 60 60 60 56 56 56 56 56 56 56 56 56 56 56 56 56 56 52 52 52 52 52 52 52 52 Fmin [MHz] 52.5 49.9 47.6 54.9 51.9 49.3 46.9 44.7 51.9 46.9 49.3 46.9 44.7 51.4 48.6 46.1 43.8 41.8 39.9 48.6 43.8 39.9 46.1 39.9 43.8 41.8 39.9 47.8 45.2 42.9 40.8 38.8 37.1 35.5 45.2 Fmax M]zH [ 82 89.1 97.6 66.1 71 76.7 83.3 91.3 71 83.3 76.7 83.3 91.3 61.6 66.1 71.4 77.6 84.9 93.8 66.1 77.6 93.8 71.4 93.8 77.6 84.9 93.8 57 61.2 66.1 71.8 78.6 86.8 96.9 61.2 (Continued) 78 DS07-16612-2E
*1
Remarks
MB91460D Series
(Continued) Modulation Degree (k) 2 2 3 3 4 5 6 7 1 1 1 1 1 1 1 2 2 2 3 3 4 5 6 7 1 1 1 1 1 1 1 2 2 2 2
Random No (N) 5 7 3 5 3 3 3 3 3 5 7 9 11 13 15 3 5 7 3 5 3 3 3 3 3 5 7 9 11 13 15 3 5 7 9
CMPR [hex] 04AC 04EA 066D 06AA 086C 0A6B 0C6A 0E69 026F 02AE 02ED 032C 036B 03AA 03E9 046E 04AC 04EA 066D 06AA 086C 0A6B 0C6A 0E69 026F 02AE 02ED 032C 036B 03AA 03E9 046E 04AC 04EA 0528
eclk saB [MHz] 52 52 52 52 52 52 52 52 48 48 48 48 48 48 48 48 48 48 48 48 48 48 48 48 44 44 44 44 44 44 44 44 44 44 44
Fmin [MHz] 40.8 37.1 42.9 37.1 40.8 38.8 37.1 35.5 44.2 41.8 39.6 37.7 35.9 34.3 32.8 41.8 37.7 34.3 39.6 34.3 37.7 35.9 34.3 32.8 40.6 38.4 36.4 34.6 33 31.5 30.1 38.4 34.6 31.5 28.9
Fmax M]zH [ 71.8 86.8 66.1 86.8 71.8 78.6 86.8 96.9 52.5 56.4 60.9 66.1 72.3 79.9 89.1 56.4 66.1 79.9 60.9 79.9 66.1 72.3 79.9 89.1 48.1 51.6 55.7 60.4 66.1 73 81.4 51.6 60.4 73 92.1
Remarks
*1
(Continued) DS07-16612-2E 79
MB91460D Series
(Continued) Modulation Degree (k) 3 3 4 4 5 6 7 8 1 1 1 1 1 1 1 2 2 2 2 3 3 3 4 4 5 6 7 8 9 1 1 1 1 1 1
Random No (N) 3 5 3 5 3 3 3 3 3 5 7 9 11 13 15 3 5 7 9 3 5 7 3 5 3 3 3 3 3 3 5 7 9 11 13
CMPR [hex] 066D 06AA 086C 08A8 0A6B 0C6A 0E69 1068 026F 02AE 02ED 032C 036B 03AA 03E9 046E 04AC 04EA 0528 066D 06AA 06E7 086C 08A8 0A6B 0C6A 0E69 1068 1267 026F 02AE 02ED 032C 036B 03AA
Baseclk [MHz] 44 44 44 44 44 44 44 44 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 36 36 36 36 36 36
Fmin [MHz] 36.4 31.5 34.6 28.9 33 31.5 30.1 28.9 37 34.9 33.1 31.5 30 28.7 27.4 34.9 31.5 28.7 26.3 33.1 28.7 25.3 31.5 26.3 30 28.7 27.4 26.3 25.3 33.3 31.5 29.9 28.4 27.1 25.8
Fmax [MHz] 55.7 73 60.4 92.1 66.1 73 81.4 92.1 43.6 46.8 50.5 54.8 59.9 66.1 73.7 46.8 54.8 66.1 83.3 50.5 66.1 95.8 54.8 83.3 59.9 66.1 73.7 83.3 95.8 39.2 42 45.3 49.2 53.8 59.3
Remarks
(Continued) 80 DS07-16612-2E
MB91460D Series
(Continued) Modulation Degree (k) 1 2 2 2 2 3 3 3 4 4 5 6 7 8 9 1 1 1 1 1 1 1 2 2 2 2 2 3 3 3 4 4 5 5 6
Random No (N) 15 3 5 7 9 3 5 7 3 5 3 3 3 3 3 3 5 7 9 11 13 15 3 5 7 9 11 3 5 7 3 5 3 5 3
CMPR [hex] 03E9 046E 04AC 04EA 0528 066D 06AA 06E7 086C 08A8 0A6B 0C6A 0E69 1068 1267 026F 02AE 02ED 032C 036B 03AA 03E9 046E 04AC 04EA 0528 0566 066D 06AA 06E7 086C 08A8 0A6B 0AA6 0C6A
eclk saB [MHz] 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32
Fmin [MHz] 24.7 31.5 28.4 25.8 23.7 29.9 25.8 22.8 28.4 23.7 27.1 25.8 24.7 23.7 22.8 29.7 28 26.6 25.3 24.1 23 22 28 25.3 23 21.1 19.5 26.6 23 20.3 25.3 21.1 24.1 19.5 23
Fmax M]zH [ 66.1 42 49.2 59.3 74.7 45.3 59.3 85.8 49.2 74.7 53.8 59.3 66.1 74.7 85.8 34.7 37.3 40.2 43.6 47.7 52.5 58.6 37.3 43.6 52.5 66.1 89.1 40.2 52.5 75.9 43.6 66.1 47.7 89.1 52.5
Remarks
(Continued) DS07-16612-2E 81
MB91460D Series
(Continued) Modulation Degree (k) 7 8 9 10
Random No (N) 3 3 3 3
CMPR [hex] 0E69 1068 1267 1466
Baseclk [MHz] 32 32 32 32
Fmin [MHz] 22 21.1 20.3 19.5
Fmax [MHz] 58.6 66.1 75.9 89.1
Remarks
*1 These settings are not possible at MB91F467Dx
82
DS07-16612-2E
MB91460D Series
SCIT RE A H L
1. Absolute maxi r Ig
Par met Power supply slew rate Power supply voltage 1*
1
Symbol VDD5R VDD5 HVDD5 VDD35 HVDD5
RatiIg IiM - 0.3 - 0.3 - 0.3 - 0.3 VDD5-0.3 VSS5-0.3 M xa 50 + 6.0 + 6.0 + 6.0 + 6.0 VDD5+0.3 VDD5+0.3
UIit V/ms V V V V V V
Remarks
Power supply voltage 2*1 Power supply voltage 3*1 Power supply voltage 4*1
SMC mode General purpose port mode At least one pin of the Ports 25 to 29 (SMC, ANn) is used as digital input or output. All pins of the Ports 25 to 29 (SMC, ANn) follow the condition of VIA *2 *2
Relationship of the supply voltages AVCC5
VDD5-0.3
VDD5+0.3
V
VSS5-0.3 Analog power supply voltage*1 Analog reference power supply voltage*1 Input voltage 1*1 Input voltage 2*1 Input voltage 3*
1 1
VDD5+0.3 + 6.0 + 6.0 VDD5 + 0.3 VDD35 + 0.3 HVDD5 + 0.3 AVcc5 + 0.3 VDD5 + 0.3 VDD35 + 0.3 HVDD5 + 0.3 + 4.0 20 10 40 8 30 100 360 50 230
V V V V V V V V V V mA mA mA mA mA mA mA mA mA mA
AVCC5 AVRH5 VI1 VI2 VI3 VIA VO1 VO2 VO3 ICLAMP |ICLAMP| IOL IOLAV IOL IOLAV
- 0.3 - 0.3 Vss5 - 0.3 Vss5 - 0.3 HVss5 - 0.3 AVss5 - 0.3 Vss5 - 0.3 Vss5 - 0.3 HVss5 - 0.3 - 4.0
External bus Stepper motor controller
Analog pin input voltage* Output voltage 1* Output voltage 2* Output voltage 3*
1 1 1
External bus Stepper motor controller *3 *3 Stepper motor controller Stepper motor controller Stepper motor controller Stepper motor controller
Maximum clamp current Total maximum clamp current "L" level maximum output current*4 "L" level average output current*5 "L" level total maximum output current "L" level total average output current*6
DS07-16612-2E
83
MB91460D Series
Rating Min - 40 - 55 Max - 10 - 40 -4 - 30 - 100 - 360 - 25 - 230 1000 + 105 + 150
Parameter "H" level maximum output current*4 "H" level average output current*5 "H" level total maximum output current "H" level total average output current*6 Power consumption Operating temperature Storage temperature
Symbol IOH IOHAV IOH IOHAV PD TA Tstg
Unit mA mA mA mA mA mA mA mA mW C C
Remarks
Stepper motor controller Stepper motor controller Stepper motor controller Stepper motor controller at TA = 105 C
*1 : The parameter is based on VSS5 = HVSS5 = AVSS5 = 0.0 V. *2 : AVCC5 and AVRH5 must not exceed VDD5 + 0.3 V. *3 : * Use within recommended operating conditions. * Use with DC voltage (current). * +B signals are input signals that exceed the VDD5 voltage. +B signals should always be applied by connecting a limiting resistor between the +B signal and the microcontroller. * The value of the limiting resistor should be set so that the current input to the microcontroller pin does not exceed the rated value at any time, either instantaneously or for an extended period, when the +B signal is input. * Note that when the microcontroller drive current is low, such as in the low power consumption modes, the +B input potential can increase the potential at the power supply pin via a protective diode, possibly affecting other devices. * Note that if the +B signal is input when the microcontroller is off (not fixed at 0 V), power is supplied through the +B input pin; therefore, the microcontroller may partially operate. * Note that if the +B signal is input at power-on, since the power is supplied through the pin, the power-on reset may not function in the power supply voltage.
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* Do not leave +B input pins open. * Example of recommended circuit : * Input/output equivalent circuit Protective diode
VCC
Limiting resistor +B input (0 V to 16 V)
P-ch
N-ch
R
*4 : Maximum output current is defined as the value of the peak current flowing through any one of the corresponding pins. *5 : Average output current is defined as the value of the average current flowing through any one of the corresponding pins for a 100 ms period. *6 : Total average output current is defined as the value of the average current flowing through all of the corresponding pins for a 100 ms period. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
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2. Recommended operating conditions
(VSS5 = AVSS5 = 0.0 V) Parameter Symbol VDD5 VDD5R VDD35 Power supply voltage HVDD5 Value Min 3.0 3.0 3.0 4.5 3.0 3.0 TA - 40 Typ 4.7 40 10 0.6 Vsurge fRC100kHz fRC2MHz 2 50 1 100 2 200 4 Max 5.5 5.5 5.5 5.5 5.5 5.5 50 + 105 Unit V V V V V V F V/ms C ns ms ms kV kHz MHz Rdischarge = 1.5k Cdischarge = 100pF VDDCORE 1.65V Cload = 0 pF Internal regulator External bus Stepper motor controller Stepper motor controller (when all pins are used as general-purpose ports) A/D converter Use a X7R ceramic capacitor or a capacitor that has similar frequency characteristics. Remarks
AVCC5 Smoothing capacitor at VCC18C pin Power supply slew rate Operating temperature Stepper motor control slew rate Main Oscillation stabilisation time Look-up time PLL (4 MHz ->16 ...100MHz) ESD Protection (Human body model) RC Oscillator CS
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their representatives beforehand.
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VCC18C
VSS5 CS
AVSS5
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3. DC characteristics
Note: In the following tables, "VDD" means VDD35 for pins of ext. bus or HVDD5 for SMC pins or VDD5 for other pins. In the following tables, "VSS" means Hvss5 for ground Pins of the stepper motor and VSS5 for the other pins. (VDD5 = AVCC5 = 3.0 V to 5.5 V, VSS5 = AVSS5 = 0 V, TA = -40 C to + 105 C) Parameter Symbol Pin name Condition Value Min Typ Max VDD + 0.3 VDD + 0.3 VDD + 0.3 VDD + 0.3 VDD + 0.3 VDD + 0.3 VDD + 0.3 VDD + 0.3 VDD + 0.3 Unit Remarks CMOS hysteresis input 4.5 V VDD 5.5 V 3 V VDD < 4.5 V
Port inputs if CMOS Hysteresis 0.8/0.2 0.8 x VDD input is selected Port inputs if CMOS 0.7 x VDD Hysteresis 0.7/0.3 0.74 x VDD input is selected AUTOMOTIVE Hysteresis input is selected Port inputs if TTL input is selected Port inputs if CMOS Hysteresis 0.8/0.2 input is selected Port inputs if CMOS Hysteresis 0.7/0.3 input is selected Port inputs if AUTOMOTIVE Hysteresis input is selected Port inputs if TTL input is selected 0.8 x VDD 2.0 0.8 x VDD VDD - 0.3 2.5 0.8 x VDD
V V V V
VIH VIHR INITX MD_2 to MD_0 X0, X0A
Input "H" voltage
V INITX input pin (CMOS Hysteresis) Mode input pins External clock in "Oscillation mode" External clock in "Fast Clock Input mode"
V
VIHM VIHX0S
V V
VIHX0F
X0
V
VSS - 0.3
0.2 x VDD
V
VIL Input "L" voltage VILR INITX MD_2 to MD_0 X0, X0A
VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3

0.3 x VDD 0.5 x VDD 0.46 x VDD 0.8 0.2 x VDD VSS + 0.3 0.5
V V V V INITX input pin (CMOS Hysteresis) Mode input pins External clock in "Oscillation mode" DS07-16612-2E 4.5 V VDD 5.5 V 3 V VDD < 4.5 V
V
VILM VILXDS 88
V V
MB91460D Series
(VDD5 = AVCC5 = 3.0 V to 5.5 V, VSS5 = AVSS5 = 0 V, TA = -40 C to + 105 C) Parameter Symbol Input "L" voltage Pin name X0 Condition Value Min VSS - 0.3 Typ Max 0.2 x VDD Unit Remarks External clock in "Fast Clock Input mode" Driving strength set to 2 mA
VILXDF
V
VOH2
4.5V VDD 5.5V, Normal IOH = - 2mA outputs 3.0V VDD 4.5V, IOH = - 1.6mA 4.5V VDD 5.5V, IOH = - 5mA Normal outputs 3.0V VDD 4.5V, IOH = - 3mA I2C 3.0V VDD 5.5V, outputs IOH = - 3mA 4.5V VDD 5.5V, TA = -40 C, High IOH = -40mA current 4.5V VDD 5.5V, outputs IOH = -30mA 3.0V VDD 4.5V, IOH = -20mA 4.5V VDD 5.5V, Normal IOH = + 2mA outputs 3.0V VDD 4.5V, IOH = + 1.6mA 4.5V VDD 5.5V, Normal IOH = + 5mA outputs 3.0V VDD 4.5V, IOH = + 3mA I2C 3.0V VDD 5.5V, outputs IOH = + 3mA 4.5V VDD 5.5V, TA = -40 C, IOH = +40mA
VDD - 0.5
V
VOH5 Output "H" voltage
VDD - 0.5
V
Driving strength set to 5 mA
VOH3
VDD - 0.5
V
See note *1
VOH30
VDD - 0.5
V
Driving strength set to 30mA
VOL2
0.4
V
Driving strength set to 2 mA
VOL5 Output "L" voltage
0.4
V
Driving strength set to 5 mA
VOL3
0.4
V
See note *2
VOL30
High current 4.5V VDD 5.5V, outputs IOH = +30mA 3.0V VDD 4.5V, IOH = +20mA
0.5
V
Driving strength set to 30mA
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Pin name Value Min -1 Typ Max +1 A -3 -1 -3 40 25 40 25 100 50 100 50 +3 +1 +3 160 100 180 100 k A A
Parameter Symbol
Condition
Unit
Remarks
Input leakage current
IIL
3.0V VDD 5.5V VSS5 < VI < VDD Pnn_m TA=25 C *3 3.0V VDD 5.5V VSS5 < VI < VDD TA=105 C 3.0V VDD 5.5V TA=25 C 3.0V VDD 5.5V TA=105 C 3.0V VDD 3.6V 4.5V VDD 5.5V 3.0V VDD 3.6V 4.5V VDD 5.5V
Analog input leakage current Pull-up resistance Pull-down resistance
IAIN
ANn *
4
RUP
Pnn_m *5 INITX Pnn_m *6
RDOWN
k
Input capacitance
CIN
All except VDD5, VDD5R, f = 1 MHz VSS5, AVCC5, AVSS, AVRH5 MB91F467Dx: CLKB: 96 MHz VDD5R CLKP: 48 MHz CLKT: 48 MHz CLKCAN: 48 MHz TA = + 25 C TA = + 105 C TA = + 25 C
-
5
15
pF
ICC
120
150
mA
Code fetch from Flash

30 400 100 500 50 450 70 50 250 20
150 2000 500 2400 250 2200 150 100 500 40
A A A A A A A A A A
At stop mode *7
*8
Power supply current MB91F467Dx
ICCH
VDD5R TA = + 105 C TA = + 25 C TA = + 105 C
RTC : 4 MHz mode *7
*8
RTC : 100 kHz mode *7
*8
ILVE ILVI
VDD5 VDD5R

External low voltage detection Internal low voltage detection Main clock (4 MHz) Sub clock (32 kHz) DS07-16612-2E
IOSC
VDD5
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MB91460D Series
Pin name Value Min Typ Max
Parameter Symbol
Condition
Unit
Remarks
ICC
MB91F465DA: CLKB: 100 MHz VDD5R CLKP: 50 MHz CLKT: 50 MHz CLKCAN: 50 MHz TA = + 25 C TA = + 105 C TA = + 25 C TA = + 105 C TA = + 25 C TA = + 105 C
-
110
140
mA
Code fetch from Flash
-
30 300 100 500 50 400 70 50 250 20
150 2000 500 2400 250 2200 150 100 500 40
A A A A A A A A A A
At stop mode *7 RTC : 4 MHz mode *7 RTC : 100 kHz mode *7 External low voltage detection Internal low voltage detection Main clock (4 MHz) Sub clock (32 kHz)
Power supply current MB91F465DA
ICCH
VDD5R
ILVE ILVI
VDD5 VDD5R
-
IOSC
VDD5 -
1. 2. 3. 4. 5. 6. 7. 8.
I2C Spec on MB91F467Dx only guaranteed for 4.5 V < VDD5 < 5.5 V. I2C Spec on MB91F467Dx only guaranteed for 4.5 V < VDD5 < 5.5 V. Pnn_m includes all GPIO pins. Analog (AN) channels and PullUp/PullDown are disabled. ANn includes all pins where AN channels are enabled. Pnn_m includes all GPIO pins. The pull up resistors must be enabled by PPER/PPCR setting and the pins must be in input direction. Pnn_m includes all GPIO pins. The pull down resistors must be enabled by PPER/PPCR setting and the pins must be in input direction. Main regulator OFF, sub regulator set to 1.2V, Low voltage detection disabled. On MB91F467Dx, the I2C pin consumes typical 200 A and maximal 400 A when "L" level is output, even if there is no load condition. When entering the standby mode while I2C outputs "L", the abovementioned current is added to ICCH. The I2C pins are recommended to use for port input or external interrupt in standby mode.
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4. A/D converter characteristics
(VDD5 = AVCC5 = 3.0 V to 5.5 V, VSS5 = AVSS5 = 0 V, TA = -40 C to + 105 C) Parameter Resolution Total error Nonlinearity error Differential nonlinearity error Zero reading voltage Full scale reading voltage Symbol Pin name VOT VFST ANn ANn Value Min -3 - 2.5 - 1.9 AVRL- 1.5 LSB AVRH- 3.5 LSB 0.6 Compare time Tcomp 2.0 s s Typ AVRL + 0.5 LSB AVRH- 1.5 LSB Max 10 +3 + 2.5 + 1.9 AVRL + 2.5 LSB AVRH + 0.5 LSB 16,500 Unit bit LSB LSB LSB V V s 4.5 V AVCC5 5.5 V 3.0 V AVCC5 4.5 V 4.5 V AVCC5 5.5 V, REXT < 2 k 3.0 V AVCC5 4.5 V, REXT < 1 k 4.5 V AVCC5 5.5 V 3.0 V AVCC5 4.5 V 4.5 V AVCC5 5.5 V 3.0 V AVCC5 4.5 V TA = + 25 C TA = + 105 C Remarks
0.4 Sampling time Tsamp 1.0

11 2.6 12.1 +1 +3 AVRH 4
s s s pF k k A A V LSB
1.0 Conversion time Tconv 3.0 Input capacitance CIN ANn Input resistance RIN ANn Analog input leakage current Analog input voltage range Offset between input channels IAIN VAIN ANn ANn ANn -1 -3 AVRL
(Continued) Note : The accuracy gets worse as AVRH - AVRL becomes smaller
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(Continued) Parameter Symbol Pin name AVRH Reference voltage range AVRL IA Power supply current IAH IR Reference voltage current IRH AVRH5 5 A AVCC5 AVRH5 0.7 5 1 A mA AVSS5 AVCC5 AVRH5 Value Min 0.75 x AVCC5 AVSS5 Typ 2.5 Max AVCC5 AVCC5 x 0.25 5 Unit V V mA A/D Converter active A/D Converter not operated *1 A/D Converter active A/D Converter not operated *2 Remarks
*1 : Supply current at AVCC5, if A/D converter and ALARM comparator are not operating, (VDD5 = AVCC5 = AVRH = 5.0 V) *2 : Input current at AVRH5, if A/D converter is not operating, (VDD5 = AVCC5 = AVRH = 5.0 V) Sampling Time Calculation Tsamp = ( 2.6 kOhm + REXT) x 11pF x 7; for 4.5V AVCC5 5.5V Tsamp = (12.1 kOhm + REXT) x 11pF x 7; for 3.0V AVCC5 4.5V Conversion Time Calculation Tconv = Tsamp + Tcomp Definition of A/D converter terms * Resolution Analog variation that is recognizable by the A/D converter. * Nonlinearity error Deviation between actual conversion characteristics and a straight line connecting the zero transition point (00 0000 0000B 00 0000 0001B) and the full scale transition point (11 1111 1110B 11 1111 1111B). * Differential nonlinearity error Deviation of the input voltage from the ideal value that is required to change the output code by 1 LSB. * Total error This error indicates the difference between actual and theoretical values, including the zero transition error, full scale transition error, and nonlinearity error.
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Total error
3FFH 3FEH 3FDH 1.5 LSB'
Actual conversion characteristics
{1 LSB' (N - 1) + 0.5 LSB'}
Digital output
004H
VNT
003H 002H 001H 0.5 LSB' AVSS5 AVRH
(measurement value) Actual conversion characteristics
Ideal characteristics
Analog input
1LSB' (ideal value) = AVRH - AVSS5 [V] 1024 Total error of digital output N = VNT - {1 LSB' x (N - 1) + 0.5 LSB'} 1 LSB' N : A/D converter digital output value VOT' (ideal value) = AVSS5 + 0.5 LSB' [V] VFST' (ideal value) = AVRH - 1.5 LSB' [V] VNT : Voltage at which the digital output changes from (N + 1) H to NH (Continued)
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(Continued)
Nonlinearity error
3FFH 3FEH {1 LSB (N - 1) + VOT} 3FDH
Actual conversion characteristics
Differential nonlinearity error
Actual conversion characteristics
(N+1)H
VFST
(measurement value)
Digital output
Digital output
Ideal characteristics
NH
004H 003H 002H 001H
VNT
(measurement value)
(N-1)H
VFST VNT
(measurement value)
Actual conversion characteristics
(measurement value)
Ideal characteristics
(N-2)H
VTO (measurement value)
AVSS5 AVRH AVSS5
Actual conversion characteristics
AVRH
Analog input
Analog input
Nonlinearity error of digital output N =
VNT - {1LSB x (N - 1) + VOT} [LSB] 1LSB V (N + 1) T - VNT 1LSB - 1 [LSB]
Differential nonlinearity error of digital output N = 1LSB = VFST - VOT 1022 [V]
N : A/D converter digital output value VOT : Voltage at which the digital output changes from 000H to 001H. VFST : Voltage at which the digital output changes from 3FEH to 3FFH.
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5. Alarm comparator characteristics
Parameter Symbol Pin name Value Min Typ Max Unit Remarks Alarm comparator enabled in fast mode (per channel) *1 Alarm comparator enabled in normal mode (per channel)
*1
IA5ALMF
25
40
A
Power supply current
AVCC5 IA5ALMS 7 10 A
IA5ALMH ALARM pin input current ALARM pin input voltage range Alarm upper limit voltage Alarm lower limit voltage Alarm hysteresis voltage Alarm input resistance IALIN
-1 -3 0 AVCC5 x 0.78 - 3% AVCC5 x 0.36 - 5% ALARM_n 50

5 +1 +3 AVCC5 AVCC5 x 0.78 + 3% AVCC5 x 0.36 + 5% 250 0.2
A A A V
Alarm comparator disabled TA=25 C TA=105 C
VALIN
VIAH
AVCC5 x 0.78
V
VIAL
AVCC5 x 0.36
V
VIAHYS
0.1
mV
RIN
5
M s Alarm comparator enabled in fast mode *1 Alarm comparator enabled in normal mode
*1
tCOMPF Comparison time tCOMPS
1
2
s
Note: *1 :
The fast Alarm Comparator mode is enabled by setting ACSR.MD=1 Setting ACSR.MD=0 sets the normal mode.
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6. FLASH memory program/erase characteristics 6.1. MB91F465DA
Value Min Typ 0.9 n*0.9 23 Max 3.6 n*3.6 370
(TA = 25oC, Vcc = 5.0V)
Parameter Sector erase time Chip erase time Word (16-bit width) programming time Flash data retention time Unit s s s cycle year *1 Remarks Erasure programming time not included n is the number of Flash sector of the device System overhead time not included
Programme/Erase cycle 10 000 20
*1: This value was converted from the results of evaluating the reliability of the technology (using Arrhenius equation to convert high temperature measurements into normalized value at 85oC)
6.2.
MB91F467Dx
Value Min Typ 0.5 n*0.5 6 Max 2.0 n*2.0 100
(TA = 25oC, Vcc = 5.0V)
Parameter Sector erase time Chip erase time Word (16 or 32-bit width) programming time Flash data retention time Unit s s s cycle year *1 Remarks Erasure programming time not included n is the number of Flash sector of the device System overhead time not included
Programme/Erase cycle 10 000 20
*1: This value was converted from the results of evaluating the reliability of the technology (using Arrhenius equation to convert high temperature measurements into normalized value at 85oC)
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7. AC characteristics 7.1. Clock timing
(VDD5 = 3.0 V to 5.5 V, Vss5 = AVss5 = 0 V, TA = -40 C to + 105 C) Parameter Symbol Pin name X0 X1 X0A X1A Value Min 3.5 32 Typ 4 32.768 Max 16 100 Unit MHz kHz Condition Opposite phase external supply or crystal
Clock frequency
fC
* Clock timing condition
tC
X0, X1, X0A, X1A
PWH PWL
0.8 VCC 0.2 VCC
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7.3. LIN-USART Timings at V
DD5
= 3.0 to 5.5 V
* Conditions during AC measurements * All AC tests were measured under the following conditions: * - IOdrive = 5 mA * - VDD5 = 3.0 V to 5.5 V, Iload = 3 mA * - VSS5 = 0 V * - Ta = -40 C to +105 C * - Cl = 50 pF (load capacity value of pins when testing) * - VOL = 0.2 x VDD5 * - VOH = 0.8 x VDD5 * - EPILR = 0, PILR = 1 (Automotive Level = worst case) (VDD5 = 3.0 V to 5.5 V, VSS5 = AVSS5 = 0 V, TA = -40 C to + 105 C) Parameter Serial clock cycle time SCK SOT delay time SOT SCK delay time Valid SIN SCK setup time SCK valid SIN hold time Serial clock "H" pulse width Serial clock "L" pulse width SCK SOT delay time Valid SIN SCK setup time SCK valid SIN hold time SCK rising time SCK falling time Symbol tSCYCI tSLOVI tOVSHI tIVSHI tSHIXI tSHSLE tSLSHE tSLOVE tIVSHE tSHIXE tFE tRE Pin name SCKn SCKn SOTn SCKn SOTn SCKn SINn SCKn SINn SCKn SCKn SCKn SOTn SCKn SINn SCKn SINn SCKn SCKn External clock operation (slave mode) Internal clock operation (master mode) Condition VDD5 = 3.0 V to 4.5 V V Min 4 tCLKP - 30 mx tCLKP - 30* tCLKP + 55 0 tCLKP + 10 tCLKP + 10 10 tCLKP + 10 Max 30 2 tCLKP + 55 20 20 Min
DD
5 = 4.5 V to 5.5 V Max
Unit ns ns ns ns ns ns ns ns ns ns ns ns
4 tCLKP - 20 mx tCLKP - 20* tCLKP + 45 0 tCLKP + 10 tCLKP + 10 10 tCLKP + 10
20 2 tCLKP + 45 20 20
* : Parameter m depends on tSCYCI and can be calculated as : * if tSCYCI = 2*k*tCLKP, then m = k, where k is an integer > 2 * if tSCYCI = (2*k + 1)*tCLKP, then m = k + 1, where k is an integer > 1 Notes : * The above values are AC characteristics for CLK synchronous mode. * tCLKP is the cycle time of the peripheral clock.
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Sr
tr
S
P
S
tf
SDA
tBUF tHD;DAT tSU;DAT tHD;STA tSU;STA tSP tSU;ST0
tHD;STA
SCL
tLOW tHIGH
tf
tr
MB91460D Series
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MB91460D Series
7.5. Free-run timer clock
(VDD5 = 3.0 V to 5.5 V, VSS5 = AVSS5 = 0 V, TA = -40 C to + 105 C) Parameter Input pulse width Symbol tTIWH tTIWL Pin name CKn Condition Value Min 4tCLKP Max Unit ns
Note : tCLKP is the cycle time of the peripheral clock.
CKn
VIH
VIH VIL
tTIWH tTIWL
VIL
7.6.
Trigger input timing
(VDD5 = 3.0 V to 5.5 V, VSS5 = AVSS5 = 0 V, TA = -40 C to + 105 C) Parameter Symbol tINP tATGX Pin name ICUn ATGX Condition Value Min 5tCLKP 5tCLKP Max Unit ns ns
Input capture input trigger A/D converter trigger
Note : tCLKP is the cycle time of the peripheral clock.
tATGX, tINP
ICUn, ATGX
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tCLCH
tCHCL
tCYC
MCLKO
tCLCSL tCLCSH
CSXn
tCHCSL
delaved CSXn
tCLASH tCLASL
ASX
tCLAV
ADDRESS
tCLBAH tCLBAL
BAAX
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MCLKO
MCLKI
tCLCSL
tCLCSH
CSXn
tCLWRL
tCLWRH
WRXn (as byte enable)
tCHRH tCHRL
RDX
tDSRH
tRHDX
tDSCH
tCHDX
DATA IN
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7.7.3. Synchronous/Asynchronous read access with internal MCLKO --> MCLKI feedback
(VDD35 = 4.5 V to 5.5 V, Vss5 = AVss5 = 0 V, TA = -40 C to + 105 C) Parameter MCLKO to RDX delay time Data valid to RDX setup time RDX to Data valid hold time (internal MCLKO MCLKI / /MCLKI feedback) MCLKO to WRXn (as byte enable) delay time MCLKO to CSXn delay time Symbol TCHRL TCHRH TDSRH Pin name MCLKO RDX RDX D31 to D0 RDX D31 to D0 MCLKO WRXn MCLKO CSXn Value Min -5 -5 20 Max 2 2 9 9 8 Unit ns ns ns
TRHDX TCLWRL TCLWRH TCLCSL TCLCSH
0 -1
ns ns ns ns ns
MCLKO
TCLCSL TCLCSH
CSXn
TCLWRL
TCLWRH
WRXn (as byte enable)
TCHRH TCHRL
RDX
TDSRH
TRHDX
DATA IN
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7.7.7. Asynchronous write access - no byte control type
(VDD35 = 4.5 V to 5.5 V, Vss5 = AVss5 = 0 V, TA = -40 C to + 105 C) Parameter WRXn to WRXn pulse width Data valid to WRXn setup time WRXn to Data valid hold time WRXn to CSXn delay time Symbol TWRLWRH TDSWRL TWRHDH TCLWRL TWRHCH Pin name WRXn WRXn D31 to D0 WRXn D31 to D0 WRXn CSXn Value Min tCLKT - 1 1/2 x tCLKT - 14 1/2 x tCLKT - 7 1/2 x tCLKT - 3 Max 1/2 x tCLKT - 1 Unit ns ns ns ns ns
CSXn
TCLWRL TWRLWRH TWRHCH
WRXn
TDSWRL
TWRHDH
DATA OUT
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7.7.8. RDY waitcycle insertion
(VDD35 = 4.5 V to 5.5 V, Vss5 = AVss5 = 0 V, TA = -40 C to + 105 C) Parameter RDY setup time RDY hold time Symbol TRDYS TRDYH Pin name MCLKO RDY MCLKO RDY Value Min 21 0 Max Unit ns ns
MCLKO
TRDYS
TRDYH
RDY
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7.7.9. Bus hold timing
(VDD35 = 4.5 V to 5.5 V, Vss5 = AVss5 = 0 V, TA = -40 C to + 105 C) Parameter MCLKO to BGRNTX delay time Bus HIZ to BGRNTX Symbol TCLBGL TCLBGH TAXBGL Pin name MCLKO BGRNTX BGRNTX MCLK* A0 to An RDX, ASX WRXn,WEX CSXn,BAAX Value Min tCLKT - 6 Max 2 x tCLKT + 5 2 x tCLKT + 2 Unit ns ns ns
BGRNTX to Bus drive
TBGHAV
tCLKT + 8
ns
Note : BRQ must be kept High until the bus is granted (this is acknowledged by the falling edge of BGRNTX). It must be kept High as long as the bus shall be hold. After releasing the bus (BRQ set to Low) this is acknowledged by the rising edge of BGRNTX.
MCLKO
BRQ
TCLBGL TCLBGH
BGRNTX
TAXBGL
ADDR,RDX,WRX, WEX,CSXn,ASX, MCLKE,MCLKI, BAAX
TBGHAV
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7.7.11. DMA transfer
(VDD35 = 4.5 V to 5.5 V, Vss5 = AVss5 = 0 V, TA = -40 C to + 105 C) Parameter MCLKO to DACKX delay time MCLKO to DEOP delay time MCLKO to DACKX delay time (ADDR delayed CS) MCLKO to DEOP delay time (ADDR delayed CS) DREQ setup time DREQ hold time DEOTXn setup time DEOTXn hold time Symbol TCLDAL TCLDAH TCLDEL TCLDEH TCHDAL TCHDEL TDRQS TDRQH TDTXS TDTXH Pin name MCLKO DACKXn MCLKO DEOPn MCLKO DACKXn MCLKO DEOPn MCLKO DREQn MCLKO DREQn MCLKO DEOTXn MCLKO DEOTXn Value Min -4 -4 23 0 24 0 Max 9 6 8 9 3 3 Unit ns ns ns ns ns ns ns ns ns ns
Note : DREQ and DEOTX must be applied for at least 5 x tCLKT to ensure that they are really sampled and evaluated. Under best case conditions (DMA not busy) only setup and hold times are required.
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MB91460D Series
MCLKO
TCLDAL
TCLDAH
DACKX
TCLDEL
TCLDEH
DEOP
TCHDAL
delayed DACKX
TCHDEL
delayed DEOP
TDRQS
TDRQH
DREQ
TDTXS
TDTXH
DEOTX
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7.8. External Bus AC Timings at V
DD35
= 3.0 to 4.5 V
* Conditions during AC measurements All AC tests were measured under the following conditions: - IOdrive = 5 mA - VDD35 = 3.0 V to 4.5 V, Iload = 3 mA - VSS5 = 0 V - Ta = - 40 C to + 105 C - Cl = 50 pF - VOL = 0.2 x VDD35 - VOH = 0.8 x VDD35 - EPILR = 0, PILR = 1 (Automotive Level = worst case)
7.8.1.
Basic Timing
(VDD35 = 3.0 V to 4.5 V, Vss5 = AVss5 = 0 V, TA = -40 C to + 105 C) Parameter Symbol TCLCH TCHCL TCLCSL TCLCSH TCHCSL TCLASL TCLASH TCLBAL TCLBAH TCLAV MCLKO ASX MCLKO BAAX MCLKO A25 to A0 MCLKO CSXn Pin name MCLKO Value Min 1/2 x tCLKT - 13 1/2 x tCLKT - 13 - 11 1 Max 1/2 x tCLKT + 13 1/2 x tCLKT + 13 6 7 0 6 9 3 13 Unit ns ns ns ns ns ns ns ns ns ns
MCLKO MCLKO to CSXn delay time MCLKO to CSXn delay time (Addr CS delay) MCLKO to ASX delay time MCLKO to BAAX delay time MCLKO to Address valid delay time
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7.8.3. Synchronous/Asynchronous read access with internal MCLKO --> MCLKI feedback
(VDD35 = 3.0 V to 4.5 V, Vss5 = AVss5 = 0 V, TA = -40 C to + 105 C) Parameter MCLKO to RDX delay time Data valid to RDX setup time RDX to Data valid hold time (internal MCLKO MCLKI / /MCLKI feedback) MCLKO to WRXn (as byte enable) delay time MCLKO to CSXn delay time Symbol TCHRL TCHRH TDSRH Pin name MCLKO RDX RDX D31 to D0 RDX D31 to D0 MCLKO WRXn MCLKO CSXn Value Min - 12 -9 29 Max 0 1 6 6 7 Unit ns ns ns
TRHDX TCLWRL TCLWRH TCLCSL TCLCSH
0 0
ns ns ns ns ns
MCLKO
TCLCSL TCLCSH
CSXn
TCLWRL
TCLWRH
WRXn (as byte enable)
TCHRH TCHRL
RDX
TDSRH
TRHDX
DATA IN
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7.8.4. Synchronous write access - byte control type
(VDD35 = 3.0 V to 4.5 V, Vss5 = AVss5 = 0 V, TA = -40 C to + 105 C) Parameter MCLKO to WEX delay time Data valid to WEX setup time WEX to Data valid hold time MCLKO to WRXn (as byte enable) delay time MCLKO to CSXn delay time Symbol TCLWL TCLWH TDSWL TWHDH TCLWRL TCLWRH TCLCSL TCLCSH Pin name MCLKO WEX WEX D31 to D0 WEX D31 to D0 MCLKO WRXn MCLKO CSXn Value Min 1 - 20 tCLKT - 19 0 Max 7 6 6 7 Unit ns ns ns ns ns ns ns ns
MCLKO
TCLCSL
TCLCSH
CSXn
TCLWRL
TCLWRH
WRXn (as byte enable)
TCLWH TCLWL
WEX
TDSWL
TWHDH
DATA OUT
MB91460D Series
7.8.5. Synchronous write access - no byte control type
(VDD35 = 3.0 V to 4.5 V, Vss5 = AVss5 = 0 V, TA = -40 C to + 105 C) Parameter MCLKO to WRXn delay time Data valid to WRXn setup time WRXn to Data valid hold time MCLKO to CSXn delay time Symbol TCLWRL TCLWRH TDSWRL TWRHDH TCLCSL TCLCSH Pin name MCLKO WRXn WRXn D31 to D0 WRXn D31 to D0 MCLKO CSXn Value Min 0 - 20 tCLKT - 14 Max 6 6 7 Unit ns ns ns ns ns ns
MCLKO
TCLCSL
TCLCSH
CSXn
TCLWRH TCLWRL
WRXn
TDSWRL
TWRHDH
DATA OUT
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7.8.6. Asynchronous write access - byte control type
(VDD35 = 3.0 V to 4.5 V, Vss5 = AVss5 = 0 V, TA = -40 C to + 105 C) Parameter WEX to WEX pulse width Data valid to WEX setup time WEX to Data valid hold time WEX to WRXn delay time WEX to CSXn delay time Symbol TWLWH TDSWL TWHDH TWRLWL TWHWRH TCLWL TWHCH Pin name WEX WEX D31 to D0 WEX D31 to D0 WEX WRXn WEX CSXn Value Min tCLKT - 2 1/2 x tCLKT - 20 1/2 x tCLKT - 20 1/2 x tCLKT - 7 1/2 x tCLKT - 4 Max 1/2 x tCLKT + 3 1/2 x tCLKT - 1 Unit ns ns ns ns ns ns ns
CSXn
TCLWL TWHCH
WRXn (as byte enable)
TWRLWL TWLWH TWHWRH
WEX
TDSWL
TWHDH
DATA OUT
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7.8.7. Asynchronous write access - no byte control type
(VDD35 = 3.0 V to 4.5 V, Vss5 = AVss5 = 0 V, TA = -40 C to + 105 C) Parameter WRXn to WRXn pulse width Data valid to WRXn setup time WRXn to Data valid hold time WRXn to CSXn delay time Symbol TWRLWRH TDSWRL TWRHDH TCLWRL TWRHCH Pin name WRXn WRXn D31 to D0 WRXn D31 to D0 WRXn CSXn Value Min tCLKT - 2 1/2 x tCLKT - 21 1/2 x tCLKT - 18 1/2 x tCLKT - 4 Max 1/2 x tCLKT - 1 Unit ns ns ns ns ns
CSXn
TCLWRL TWRLWRH TWRHCH
WRXn
TDSWRL
TWRHDH
DATA OUT
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7.8.8. RDY waitcycle insertion
(VDD35 = 3.0 V to 4.5 V, Vss5 = AVss5 = 0 V, TA = -40 C to + 105 C) Parameter RDY setup time RDY hold time Symbol TRDYS TRDYH Pin name MCLKO RDY MCLKO RDY Value Min 37 0 Max Unit ns ns
MCLKO
TRDYS
TRDYH
RDY
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7.8.9. Bus hold timing
(VDD35 = 3.0 V to 4.5 V, Vss5 = AVss5 = 0 V, TA = -40 C to + 105 C) Parameter MCLKO to BGRNTX delay time Bus HIZ to BGRNTX Symbol TCLBGL TCLBGH TAXBGL Pin name MCLKO BGRNTX BGRNTX MCLK* A0 to An RDX, ASX WRXn,WEX CSXn,BAAX Value Min tCLKT + 1 Max 2 x tCLKT + 16 2 x tCLKT + 3 Unit ns ns ns
BGRNTX to Bus drive
TBGHAV
tCLKT + 1
ns
Note : BRQ must be kept High until the bus is granted (this is acknowledged by the falling edge of BGRNTX). It must be kept High as long as the bus shall be hold. After releasing the bus (BRQ set to Low) this is acknowledged by the rising edge of BGRNTX.
MCLKO
BRQ
TCLBGL TCLBGH
BGRNTX
TAXBGL
ADDR,RDX,WRX, WEX,CSXn,ASX, MCLKE,MCLKI, BAAX
TBGHAV
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7.8.10. Clock relationships
(VDD35 = 3.0 V to 4.5 V, Vss5 = AVss5 = 0 V, TA = -40 C to + 105 C) Parameter MCLKO to MCLKE (in sleep mode) Symbol TCLML TCLMH Pin name MCLKO MCLKE Value Min 0 Max 3 Unit ns ns
MCLKO
TCLML
TCLMH
MCLKE(sleep)
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7.8.11. DMA transfer
(VDD35 = 3.0 V to 4.5 V, Vss5 = AVss5 = 0 V, TA = -40 C to + 105 C) Parameter MCLKO to DACKX delay time MCLKO to DEOP delay time MCLKO to DACKX delay time (ADDR delayed CS) MCLKO to DEOP delay time (ADDR delayed CS) DREQ setup time DREQ hold time DEOTXn setup time DEOTXn hold time Symbol TCLDAL TCLDAH TCLDEL TCLDEH TCHDAL TCHDEL TDRQS TDRQH TDTXS TDTXH Pin name MCLKO DACKXn MCLKO DEOPn MCLKO DACKXn MCLKO DEOPn MCLKO DREQn MCLKO DREQn MCLKO DEOTXn MCLKO DEOTXn Value Min - 10 - 10 38 0 39 0 Max 7 8 7 11 2 1 Unit ns ns ns ns ns ns ns ns ns ns
Note : DREQ and DEOTX must be applied for at least 5 x tCLKT to ensure that they are really sampled and evaluated. Under best case conditions (DMA not busy) only setup and hold times are required.
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MB91460D Series
MCLKO
TCLDAL
TCLDAH
DACKX
TCLDEL
TCLDEH
DEOP
TCHDAL
delayed DACKX
TCHDEL
delayed DEOP
TDRQS
TDRQH
DREQ
TDTXS
TDTXH
DEOTX
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N O I S E MG A DK C P
208-pin plastic QFP Lead pitch Pa ckage width x package length Lead shape Sealing method Mounting height We ight 0.50 mm 28.0 x 28.0 mm Gullwing Plastic mold 3.95 mm MAX 5.71g Low heat resistance type
(FPT-208P-M04)
Remar k
208-pin plastic QFP (FPT -208P-M04)
Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder.
30.600.20(1.205.008)SQ
* 28.000.10(1.102.004)SQ
0.17
156 105
.007
104
+0.03 -0.08 +.001 -.003
157
0.08(.003)
Details of "A" par t 3.75 .148
+0.20 -0.30 +.008 -.012
(Mounting height)
0.40 INDEX 0~8
53
.016 (Stand off)
+0.10 -0.15 +.004 -.006
208
"A"
LEAD No .
1
52
0.50(.020)
0.220.05 (.009.002)
0.500.20 (.020.008) 0.600.15 (.024.006)
0.25(.010)
0.08(.003)
M
C
2003-2008 FUJITSU MICROELECTRONICS LIMITED F208020S-c-3-5
Dimensions in mm (inches). Note: The values in parentheses are reference values.
Please confirm the latest Package dimension by following URL. http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html
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Y RO TSIH N VE
Version 2.0 Date 2007-09-04 Initial version Revision history table added Fixed PDF generation problem before section "AD converter characteristics" Absolute maximum ratings: Smoothing capacitor size at VCC18C changed to "typ 4.7uF" Output voltage 2 is max. VDD35 Recommended operating conditions: Power supply slew rate fixed Exchanged the sequence of device names into "MB91F465DA, MB91F467DA" where they appeare on one line Moved revision history to the end of file Features: Added Clock Monitor Corrected VCC18C pin number in table "Power supply/Ground pins" pg.14 Remark
2.1
2007-10-08
2.2
2007-10-16
Electrical characteristics: Added section 7.FLASH memory program/erase characteristics
2.3 2007-10-22 DC characterisitcs: Corrected ICCH in STOP + RTC 100kHz mode and ILV (Icc of low volt detection) max. value
2.4
2007-10-25
FLASH memory program/erase characteristics: Typo fixed in note *1 Recommended operating conditions: Corrected text for smoothing capacitor at VCC18C pin Naming inconsistency AVSS / AVSS5 fixed Features: added Up/Down counter Product lineup: fixed number of interrupt channels Handling devices: changed the notes about external clock supply and removed section "Single phase clock supply" Clock timing: removed "Single phase clock supply" from freq. table
DC characterisitcs: IIL = +/- 3 uA at 105 deg.C IO CIRCUIT TYPE: Corrected oscillator pin block diagrams ELECTRICAL CHARACTERISTICS: re-arranged section sequence Fixed typos in ALARM comparator spec. Added MB91F467DB (called F467Dx if the text item is for bot revisions) Corrected IO-MAP according to latest proofread on F460G series Various corrections after proofread by FJ Added MEMO and DISCLAIMER AC-Characteristics: Replaced "rising"/"falling" with arrow-up/arrow-down
2.5
2008-1-11
2.6 2.7
2008-02-04 2008-02-18
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MB91460D Series
Version Date Remark Corrected missing bullets on PDF pages 2+3 Pin Assignment, Block Diagram: Corrected naming and assignments of TTG inputs, SGO and DACKX0 Notes on PS register: Re-formatted for better understanding ADC Characteristics: Offset between ADC channels is max. 4 LSB DC Characteristics: Added ILVI (ICC of internal low voltage detection), renamed ILV into ILVE (for external low voltage detection) AC Characteristics for external bus: Added notes that the usage of external feedback MCLKO --> MCLKI is not recommended. Flash parallel programming mode: Added notes about the pins to be set fix-0 / fix-1 (MD_2:0,...) Added section about the wait times after power on Flash operation modes: Added note about the BootROM fuction entry address for operation mode switch. Package Dimension: Updated package drawing All pages: Corrected typos and formatting bugs found by FJ proofread EMBEDDED PROGRAM/DATA MEMORY (FLASH): Corrected "The operation mode of the flash memory ..." instead of "of the MCU" Resources,Product lineup: Added Supply Supervisor (Low voltage detection) DC Characteristics: Updated pull-up/pull-down resistance values, updated and re-numbered the table footnotes Interrupt Vector Table: corrected the footnotes Flash Security: Corrected the sector assignments of FSV1/FSV2 bits Electrical Characteristics: removed the note that analog input/output pins cannot accept +B signal input. Ordering information: updated the part numbers All pages: Kilobytes are now written with "K"
2.8
2008-06-20
2.9
2008-06-30
2.10
2008-08-04
2.11
2008-08-18
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REMIALCS D N O
MEMO
DS07-16612-2E
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MB91460D Series
MEMO
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MB91460D Series
FUJITSU MICROELECTRONICS LIMITED
Shinjuku Dai-Ichi Seimei Bldg., 7-1, Nishishinjuku 2-chome, Shinjuku-ku, Tokyo 163-0722, Japan Tel: +81-3-5322-3329 http://jp.fujitsu.com/fml/en/ For further information please contact: North and South America FUJITSU MICROELECTRONICS AMERICA, INC. 1250 E. Arques Avenue, M/S 333 Sunnyvale, CA 94085-5401, U.S.A. Tel: +1-408-737-5600 Fax: +1-408-737-5999 http://www.fma.fujitsu.com/ Europe FUJITSU MICROELECTRONICS EUROPE GmbH Pittlerstrasse 47, 63225 Langen, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 http://emea.fujitsu.com/microelectronics/ Korea FUJITSU MICROELECTRONICS KOREA LTD. 206 Kosmo Tower Building, 1002 Daechi-Dong, Gangnam-Gu, Seoul 135-280, Republic of Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111 http://kr.fujitsu.com/fmk/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LTD. 151 Lorong Chuan, #05-08 New Tech Park 556741 Singapore Tel : +65-6281-0770 Fax : +65-6281-0220 http://www.fmal.fujitsu.com/ FUJITSU MICROELECTRONICS SHANGHAI CO., LTD. Rm. 3102, Bund Center, No.222 Yan An Road (E), Shanghai 200002, China Tel : +86-21-6146-3688 Fax : +86-21-6335-1605 http://cn.fujitsu.com/fmc/ FUJITSU MICROELECTRONICS PACIFIC ASIA LTD. 10/F., World Commerce Centre, 11 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel : +852-2377-0226 Fax : +852-2376-3269 http://cn.fujitsu.com/fmc/en/
Specifications are subject to change without notice. For further information please contact each office. All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSU MICROELECTRONICS does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. FUJITSU MICROELECTRONICS assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU MICROELECTRONICS or any third party or does FUJITSU MICROELECTRONICS warrant non-infringement of any third-party's intellectual property right or other right by using such information. FUJITSU MICROELECTRONICS assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws. The company names and brand names herein are the trademarks or registered trademarks of their respective owners. Edited: Sales Promotion Department

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